sim_object.cc revision 10023
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 37534Ssteve.reinhardt@amd.com * Copyright (c) 2010 Advanced Micro Devices, Inc. 42SN/A * All rights reserved. 52SN/A * 62SN/A * Redistribution and use in source and binary forms, with or without 72SN/A * modification, are permitted provided that the following conditions are 82SN/A * met: redistributions of source code must retain the above copyright 92SN/A * notice, this list of conditions and the following disclaimer; 102SN/A * redistributions in binary form must reproduce the above copyright 112SN/A * notice, this list of conditions and the following disclaimer in the 122SN/A * documentation and/or other materials provided with the distribution; 132SN/A * neither the name of the copyright holders nor the names of its 142SN/A * contributors may be used to endorse or promote products derived from 152SN/A * this software without specific prior written permission. 162SN/A * 172SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 182SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 192SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 202SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 212SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 222SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 232SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 242SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 252SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 262SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 272SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 282665Ssaidi@eecs.umich.edu * 292665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 302665Ssaidi@eecs.umich.edu * Nathan Binkert 312SN/A */ 322SN/A 336216Snate@binkert.org#include <cassert> 342SN/A 35330SN/A#include "base/callback.hh" 3656SN/A#include "base/inifile.hh" 371031SN/A#include "base/match.hh" 38330SN/A#include "base/misc.hh" 39330SN/A#include "base/trace.hh" 406214Snate@binkert.org#include "base/types.hh" 418320Ssteve.reinhardt@amd.com#include "debug/Checkpoint.hh" 4210023Smatt.horsnell@ARM.com#include "sim/probe/probe.hh" 43330SN/A#include "sim/sim_object.hh" 44695SN/A#include "sim/stats.hh" 452SN/A 462SN/Ausing namespace std; 472SN/A 482SN/A 492SN/A//////////////////////////////////////////////////////////////////////// 502SN/A// 512SN/A// SimObject member definitions 522SN/A// 532SN/A//////////////////////////////////////////////////////////////////////// 542SN/A 552SN/A// 562SN/A// static list of all SimObjects, used for initialization etc. 572SN/A// 582SN/ASimObject::SimObjectList SimObject::simObjectList; 592SN/A 602SN/A// 612SN/A// SimObject constructor: used to maintain static simObjectList 622SN/A// 634762Snate@binkert.orgSimObject::SimObject(const Params *p) 649983Sstever@gmail.com : EventManager(getEventQueue(p->eventq_index)), _params(p) 652SN/A{ 661031SN/A#ifdef DEBUG 671031SN/A doDebugBreak = false; 681031SN/A#endif 691553SN/A simObjectList.push_back(this); 7010023Smatt.horsnell@ARM.com probeManager = new ProbeManager(this); 711553SN/A} 721553SN/A 73465SN/Avoid 74465SN/ASimObject::init() 75465SN/A{ 76465SN/A} 77465SN/A 787492Ssteve.reinhardt@amd.comvoid 797532Ssteve.reinhardt@amd.comSimObject::loadState(Checkpoint *cp) 807532Ssteve.reinhardt@amd.com{ 818320Ssteve.reinhardt@amd.com if (cp->sectionExists(name())) { 828320Ssteve.reinhardt@amd.com DPRINTF(Checkpoint, "unserializing\n"); 837532Ssteve.reinhardt@amd.com unserialize(cp, name()); 848320Ssteve.reinhardt@amd.com } else { 858320Ssteve.reinhardt@amd.com DPRINTF(Checkpoint, "no checkpoint section found\n"); 868320Ssteve.reinhardt@amd.com } 877532Ssteve.reinhardt@amd.com} 887532Ssteve.reinhardt@amd.com 897532Ssteve.reinhardt@amd.comvoid 907532Ssteve.reinhardt@amd.comSimObject::initState() 917532Ssteve.reinhardt@amd.com{ 927532Ssteve.reinhardt@amd.com} 937532Ssteve.reinhardt@amd.com 947532Ssteve.reinhardt@amd.comvoid 957492Ssteve.reinhardt@amd.comSimObject::startup() 967492Ssteve.reinhardt@amd.com{ 977492Ssteve.reinhardt@amd.com} 987492Ssteve.reinhardt@amd.com 992SN/A// 1002SN/A// no default statistics, so nothing to do in base implementation 1012SN/A// 1022SN/Avoid 1032SN/ASimObject::regStats() 1042SN/A{ 1052SN/A} 1062SN/A 1072SN/Avoid 108330SN/ASimObject::resetStats() 109330SN/A{ 110330SN/A} 111330SN/A 11210023Smatt.horsnell@ARM.com/** 11310023Smatt.horsnell@ARM.com * No probe points by default, so do nothing in base. 11410023Smatt.horsnell@ARM.com */ 11510023Smatt.horsnell@ARM.comvoid 11610023Smatt.horsnell@ARM.comSimObject::regProbePoints() 11710023Smatt.horsnell@ARM.com{ 11810023Smatt.horsnell@ARM.com} 11910023Smatt.horsnell@ARM.com 12010023Smatt.horsnell@ARM.com/** 12110023Smatt.horsnell@ARM.com * No probe listeners by default, so do nothing in base. 12210023Smatt.horsnell@ARM.com */ 12310023Smatt.horsnell@ARM.comvoid 12410023Smatt.horsnell@ARM.comSimObject::regProbeListeners() 12510023Smatt.horsnell@ARM.com{ 12610023Smatt.horsnell@ARM.com} 12710023Smatt.horsnell@ARM.com 12810023Smatt.horsnell@ARM.comProbeManager * 12910023Smatt.horsnell@ARM.comSimObject::getProbeManager() 13010023Smatt.horsnell@ARM.com{ 13110023Smatt.horsnell@ARM.com return probeManager; 13210023Smatt.horsnell@ARM.com} 13310023Smatt.horsnell@ARM.com 1342SN/A// 135395SN/A// static function: serialize all SimObjects. 136395SN/A// 137395SN/Avoid 1389196SAndreas.Sandberg@arm.comSimObject::serializeAll(std::ostream &os) 139395SN/A{ 140573SN/A SimObjectList::reverse_iterator ri = simObjectList.rbegin(); 141573SN/A SimObjectList::reverse_iterator rend = simObjectList.rend(); 142395SN/A 143573SN/A for (; ri != rend; ++ri) { 144573SN/A SimObject *obj = *ri; 145395SN/A obj->nameOut(os); 146395SN/A obj->serialize(os); 147395SN/A } 148395SN/A} 149843SN/A 1507492Ssteve.reinhardt@amd.com 1511031SN/A#ifdef DEBUG 1521031SN/A// 1531031SN/A// static function: flag which objects should have the debugger break 1541031SN/A// 1551031SN/Avoid 1561031SN/ASimObject::debugObjectBreak(const string &objs) 1571031SN/A{ 1581031SN/A SimObjectList::const_iterator i = simObjectList.begin(); 1591031SN/A SimObjectList::const_iterator end = simObjectList.end(); 1601031SN/A 1611031SN/A ObjectMatch match(objs); 1621031SN/A for (; i != end; ++i) { 1631031SN/A SimObject *obj = *i; 1641031SN/A obj->doDebugBreak = match.match(obj->name()); 1651031SN/A } 1661031SN/A} 1671031SN/A 1681031SN/Avoid 1691031SN/AdebugObjectBreak(const char *objs) 1701031SN/A{ 1711031SN/A SimObject::debugObjectBreak(string(objs)); 1721031SN/A} 1731031SN/A#endif 1741031SN/A 1752901Ssaidi@eecs.umich.eduunsigned int 1769342SAndreas.Sandberg@arm.comSimObject::drain(DrainManager *drain_manager) 1772797Sktlim@umich.edu{ 1789342SAndreas.Sandberg@arm.com setDrainState(Drained); 1792901Ssaidi@eecs.umich.edu return 0; 1802797Sktlim@umich.edu} 1812797Sktlim@umich.edu 1822797Sktlim@umich.edu 1835314Sstever@gmail.comSimObject * 1845314Sstever@gmail.comSimObject::find(const char *name) 1855314Sstever@gmail.com{ 1865314Sstever@gmail.com SimObjectList::const_iterator i = simObjectList.begin(); 1875314Sstever@gmail.com SimObjectList::const_iterator end = simObjectList.end(); 1885314Sstever@gmail.com 1895314Sstever@gmail.com for (; i != end; ++i) { 1905314Sstever@gmail.com SimObject *obj = *i; 1915314Sstever@gmail.com if (obj->name() == name) 1925314Sstever@gmail.com return obj; 1935314Sstever@gmail.com } 1945314Sstever@gmail.com 1955314Sstever@gmail.com return NULL; 1965314Sstever@gmail.com} 197