sim_events.hh revision 2632:1bb2f91485ea
15794SN/A/* 25794SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 35794SN/A * All rights reserved. 45794SN/A * 55794SN/A * Redistribution and use in source and binary forms, with or without 65794SN/A * modification, are permitted provided that the following conditions are 75794SN/A * met: redistributions of source code must retain the above copyright 85794SN/A * notice, this list of conditions and the following disclaimer; 95794SN/A * redistributions in binary form must reproduce the above copyright 105794SN/A * notice, this list of conditions and the following disclaimer in the 115794SN/A * documentation and/or other materials provided with the distribution; 125794SN/A * neither the name of the copyright holders nor the names of its 135794SN/A * contributors may be used to endorse or promote products derived from 145794SN/A * this software without specific prior written permission. 155794SN/A * 165794SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175794SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185794SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195794SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205794SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215794SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225794SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235794SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245794SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255794SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265794SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275794SN/A */ 285794SN/A 295794SN/A#ifndef __SIM_SIM_EVENTS_HH__ 305794SN/A#define __SIM_SIM_EVENTS_HH__ 315794SN/A 325794SN/A#include "sim/eventq.hh" 335794SN/A 345794SN/A// 355794SN/A// Event to terminate simulation at a particular cycle/instruction 365794SN/A// 375794SN/Aclass SimExitEvent : public Event 385794SN/A{ 395794SN/A private: 405794SN/A // string explaining why we're terminating 415794SN/A std::string cause; 425794SN/A int code; 435794SN/A 445794SN/A public: 455794SN/A SimExitEvent(const std::string &_cause, int c = 0) 465794SN/A : Event(&mainEventQueue, Sim_Exit_Pri), cause(_cause), 475794SN/A code(c) 485794SN/A { schedule(curTick); } 495794SN/A 505794SN/A SimExitEvent(Tick _when, const std::string &_cause, int c = 0) 515794SN/A : Event(&mainEventQueue, Sim_Exit_Pri), cause(_cause), 525794SN/A code(c) 535794SN/A { schedule(_when); } 545794SN/A 555794SN/A SimExitEvent(EventQueue *q, const std::string &_cause, int c = 0) 565794SN/A : Event(q, Sim_Exit_Pri), cause(_cause), code(c) 575794SN/A { schedule(curTick); } 585794SN/A 595794SN/A SimExitEvent(EventQueue *q, Tick _when, const std::string &_cause, 605794SN/A int c = 0) 615794SN/A : Event(q, Sim_Exit_Pri), cause(_cause), code(c) 625794SN/A { schedule(_when); } 635794SN/A 645794SN/A void process(); // process event 655794SN/A 665794SN/A virtual const char *description(); 675794SN/A}; 685794SN/A 695794SN/A// 705794SN/A// Event class to terminate simulation after 'n' related events have 715794SN/A// occurred using a shared counter: used to terminate when *all* 725794SN/A// threads have reached a particular instruction count 735794SN/A// 745794SN/Aclass CountedExitEvent : public Event 755794SN/A{ 765794SN/A private: 775794SN/A std::string cause; // string explaining why we're terminating 785794SN/A int &downCounter; // decrement & terminate if zero 795794SN/A 805794SN/A public: 815794SN/A CountedExitEvent(EventQueue *q, const std::string &_cause, 825794SN/A Tick _when, int &_downCounter); 835794SN/A 845794SN/A void process(); // process event 855794SN/A 865794SN/A virtual const char *description(); 875794SN/A}; 885794SN/A 895794SN/A// 905794SN/A// Event to check swap usage 915794SN/A// 925794SN/Aclass CheckSwapEvent : public Event 935794SN/A{ 945794SN/A private: 955794SN/A int interval; 965794SN/A 975794SN/A public: 985794SN/A CheckSwapEvent(EventQueue *q, int ival) 995794SN/A : Event(q), interval(ival) 1005794SN/A { schedule(curTick + interval); } 1015794SN/A 1025794SN/A void process(); // process event 10310905SN/A 1045794SN/A virtual const char *description(); 1055794SN/A}; 1065794SN/A 10710905SN/A// 1085794SN/A// Progress event: print out cycle every so often so we know we're 1095794SN/A// making forward progress. 1105794SN/A// 1115794SN/Aclass ProgressEvent : public Event 1125794SN/A{ 1135794SN/A protected: 11410905SN/A Tick interval; 1155794SN/A 1165794SN/A public: 1175794SN/A ProgressEvent(EventQueue *q, Tick ival) 1185794SN/A : Event(q), interval(ival) 1195794SN/A { schedule(curTick + interval); } 1205794SN/A 1215794SN/A void process(); // process event 1225794SN/A 1235794SN/A virtual const char *description(); 1245794SN/A}; 1255794SN/A 1265794SN/A#endif // __SIM_SIM_EVENTS_HH__ 1275794SN/A