root.cc revision 2665
12SN/A/*
21762SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan
32SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert
292665Ssaidi@eecs.umich.edu *          Steve Reinhardt
302SN/A */
312SN/A
32488SN/A#include <cstring>
33488SN/A#include <fstream>
342SN/A#include <list>
352SN/A#include <string>
362SN/A#include <vector>
372SN/A
38488SN/A#include "base/misc.hh"
391388SN/A#include "base/output.hh"
401310SN/A#include "sim/builder.hh"
411310SN/A#include "sim/host.hh"
421798SN/A#include "sim/sim_events.hh"
431310SN/A#include "sim/sim_object.hh"
441696SN/A#include "sim/root.hh"
452SN/A
462SN/Ausing namespace std;
472SN/A
482SN/ATick curTick = 0;
49488SN/Aostream *outputStream;
501104SN/Aostream *configStream;
51488SN/A
521609SN/A/// The simulated frequency of curTick. (This is only here for a short time)
531609SN/ATick ticksPerSecond;
541609SN/A
551609SN/Anamespace Clock {
561609SN/A/// The simulated frequency of curTick. (In ticks per second)
571609SN/ATick Frequency;
581609SN/A
591609SN/Anamespace Float {
601609SN/Adouble s;
611609SN/Adouble ms;
621609SN/Adouble us;
631609SN/Adouble ns;
641609SN/Adouble ps;
651609SN/A
661609SN/Adouble Hz;
671609SN/Adouble kHz;
681609SN/Adouble MHz;
691609SN/Adouble GHZ;
701609SN/A/* namespace Float */ }
711609SN/A
721609SN/Anamespace Int {
731609SN/ATick s;
741609SN/ATick ms;
751609SN/ATick us;
761609SN/ATick ns;
771609SN/ATick ps;
781609SN/A/* namespace Float */ }
791609SN/A
801609SN/A/* namespace Clock */ }
811609SN/A
821609SN/A
831310SN/A// Dummy Object
841310SN/Aclass Root : public SimObject
852SN/A{
861798SN/A  private:
871863SN/A    Tick max_tick;
881798SN/A    Tick progress_interval;
891798SN/A
902SN/A  public:
911863SN/A    Root(const std::string &name, Tick maxtick, Tick pi)
921863SN/A        : SimObject(name), max_tick(maxtick), progress_interval(pi)
931798SN/A    {}
941798SN/A
951798SN/A    virtual void startup();
962SN/A};
971104SN/A
981798SN/Avoid
991798SN/ARoot::startup()
1001798SN/A{
1011863SN/A    if (max_tick != 0)
1021863SN/A        new SimExitEvent(curTick + max_tick, "reached maximum cycle count");
1031798SN/A
1041798SN/A    if (progress_interval != 0)
1051798SN/A        new ProgressEvent(&mainEventQueue, progress_interval);
1061798SN/A}
1071798SN/A
1081310SN/ABEGIN_DECLARE_SIM_OBJECT_PARAMS(Root)
1091104SN/A
1101695SN/A    Param<Tick> clock;
1111863SN/A    Param<Tick> max_tick;
1121798SN/A    Param<Tick> progress_interval;
1131310SN/A    Param<string> output_file;
1141310SN/A
1151310SN/AEND_DECLARE_SIM_OBJECT_PARAMS(Root)
1161310SN/A
1171310SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(Root)
1181310SN/A
1191695SN/A    INIT_PARAM(clock, "tick frequency"),
1201863SN/A    INIT_PARAM(max_tick, "maximum simulation time"),
1211798SN/A    INIT_PARAM(progress_interval, "print a progress message"),
1221388SN/A    INIT_PARAM(output_file, "file to dump simulator output to")
1231310SN/A
1241310SN/AEND_INIT_SIM_OBJECT_PARAMS(Root)
1251310SN/A
1261310SN/ACREATE_SIM_OBJECT(Root)
1271310SN/A{
1281388SN/A    static bool created = false;
1291388SN/A    if (created)
1301388SN/A        panic("only one root object allowed!");
1311388SN/A
1321388SN/A    created = true;
1331310SN/A
1341609SN/A    outputStream = simout.find(output_file);
1351863SN/A    Root *root = new Root(getInstanceName(), max_tick, progress_interval);
1361609SN/A
1371609SN/A    using namespace Clock;
1381695SN/A    Frequency = clock;
1391609SN/A    Float::s = static_cast<double>(Frequency);
1401609SN/A    Float::ms = Float::s / 1.0e3;
1411609SN/A    Float::us = Float::s / 1.0e6;
1421609SN/A    Float::ns = Float::s / 1.0e9;
1431609SN/A    Float::ps = Float::s / 1.0e12;
1441310SN/A
1451609SN/A    Float::Hz  = 1.0 / Float::s;
1461609SN/A    Float::kHz = 1.0 / Float::ms;
1471609SN/A    Float::MHz = 1.0 / Float::us;
1481609SN/A    Float::GHZ = 1.0 / Float::ns;
1491609SN/A
1501609SN/A    Int::s  = Frequency;
1511609SN/A    Int::ms = Int::s / 1000;
1521609SN/A    Int::us = Int::ms / 1000;
1531609SN/A    Int::ns = Int::us / 1000;
1541609SN/A    Int::ps = Int::ns / 1000;
1551609SN/A
1561609SN/A    return root;
1571310SN/A}
1581310SN/A
1591310SN/AREGISTER_SIM_OBJECT("Root", Root)
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