pseudo_inst.cc revision 299
11060SN/A/*
21762SN/A * Copyright (c) 2003 The Regents of The University of Michigan
31060SN/A * All rights reserved.
41060SN/A *
51060SN/A * Redistribution and use in source and binary forms, with or without
61060SN/A * modification, are permitted provided that the following conditions are
71060SN/A * met: redistributions of source code must retain the above copyright
81060SN/A * notice, this list of conditions and the following disclaimer;
91060SN/A * redistributions in binary form must reproduce the above copyright
101060SN/A * notice, this list of conditions and the following disclaimer in the
111060SN/A * documentation and/or other materials provided with the distribution;
121060SN/A * neither the name of the copyright holders nor the names of its
131060SN/A * contributors may be used to endorse or promote products derived from
141060SN/A * this software without specific prior written permission.
151060SN/A *
161060SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
171060SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
181060SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
191060SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
201060SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
211060SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
221060SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
231060SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
241060SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
251060SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
261060SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu */
282665Ssaidi@eecs.umich.edu
291060SN/A#include <string>
301060SN/A
311464SN/A#include "arch/alpha/pseudo_inst.hh"
321464SN/A#include "cpu/exec_context.hh"
331060SN/A#include "sim/param.hh"
342292SN/A#include "sim/serialize.hh"
351464SN/A#include "sim/sim_exit.hh"
361060SN/A#include "sim/sim_stats.hh"
372669Sktlim@umich.edu
381060SN/Ausing namespace std;
391060SN/Ausing namespace Statistics;
401858SN/A
411464SN/Anamespace AlphaPseudo
421464SN/A{
432669Sktlim@umich.edu    bool doStatisticsInsts;
441060SN/A    bool doCheckpointInsts;
452669Sktlim@umich.edu
462292SN/A    void
472292SN/A    m5exit_old(ExecContext *xc)
481717SN/A    {
491717SN/A        SimExit(curTick, "m5_exit_old instruction encountered");
501717SN/A    }
511717SN/A
522292SN/A    void
531060SN/A    m5exit(ExecContext *xc)
541060SN/A    {
551060SN/A        Tick delay = xc->regs.intRegFile[16];
561060SN/A        Tick when = curTick + NS2Ticks(delay);
571060SN/A        SimExit(when, "m5_exit instruction encountered");
581060SN/A    }
591061SN/A
601061SN/A    void
611060SN/A    resetstats(ExecContext *xc)
621060SN/A    {
631061SN/A        if (!doStatisticsInsts)
641060SN/A            return;
651060SN/A
661060SN/A        Tick delay = xc->regs.intRegFile[16];
671060SN/A        Tick period = xc->regs.intRegFile[17];
682292SN/A
691060SN/A        Tick when = curTick + NS2Ticks(delay);
702292SN/A        Tick repeat = NS2Ticks(period);
712107SN/A
722292SN/A        SetupEvent(Reset, when, repeat);
732292SN/A    }
742292SN/A
752107SN/A    void
762292SN/A    dumpstats(ExecContext *xc)
772107SN/A    {
781060SN/A        if (!doStatisticsInsts)
792292SN/A            return;
802292SN/A
812292SN/A        Tick delay = xc->regs.intRegFile[16];
822292SN/A        Tick period = xc->regs.intRegFile[17];
832292SN/A
842292SN/A        Tick when = curTick + NS2Ticks(delay);
851060SN/A        Tick repeat = NS2Ticks(period);
862292SN/A
872292SN/A        SetupEvent(Dump, when, repeat);
881060SN/A    }
891060SN/A
902292SN/A    void
912107SN/A    dumpresetstats(ExecContext *xc)
921060SN/A    {
931060SN/A        if (!doStatisticsInsts)
941060SN/A            return;
951060SN/A
961060SN/A        Tick delay = xc->regs.intRegFile[16];
971060SN/A        Tick period = xc->regs.intRegFile[17];
982292SN/A
991060SN/A        Tick when = curTick + NS2Ticks(delay);
1001060SN/A        Tick repeat = NS2Ticks(period);
1012292SN/A
1022292SN/A        SetupEvent(Dump|Reset, when, repeat);
1032292SN/A    }
1042292SN/A
1052292SN/A    void
1062292SN/A    m5checkpoint(ExecContext *xc)
1072292SN/A    {
1081060SN/A        if (!doCheckpointInsts)
1092132SN/A            return;
1101060SN/A
1112292SN/A        Tick delay = xc->regs.intRegFile[16];
1122292SN/A        Tick period = xc->regs.intRegFile[17];
1132292SN/A
1142292SN/A        Tick when = curTick + NS2Ticks(delay);
1152292SN/A        Tick repeat = NS2Ticks(period);
1162292SN/A
1172292SN/A        SetupCheckpoint(when, repeat);
1182292SN/A    }
1191060SN/A
1202132SN/A    class Context : public ParamContext
1211060SN/A    {
1221060SN/A      public:
1231060SN/A        Context(const string &section) : ParamContext(section) {}
1241060SN/A        void checkParams();
1252132SN/A    };
1262132SN/A
1271060SN/A    Context context("PseudoInsts");
1281684SN/A
1291060SN/A    Param<bool> __statistics(&context, "statistics", "yes");
1301060SN/A    Param<bool> __checkpoint(&context, "checkpoint", "yes");
1311060SN/A
1321060SN/A    void
1332292SN/A    Context::checkParams()
1342292SN/A    {
1352292SN/A        doStatisticsInsts = __statistics;
1362292SN/A        doCheckpointInsts = __checkpoint;
1372292SN/A    }
1382292SN/A}
1392292SN/A