pseudo_inst.cc revision 2799:1c93aed5aa4a
16019Shines@cs.fsu.edu/* 210037SARM gem5 Developers * Copyright (c) 2003-2006 The Regents of The University of Michigan 37093Sgblack@eecs.umich.edu * All rights reserved. 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 67093Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 77093Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 87093Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 97093Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 107093Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 117093Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 127093Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 137093Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 146019Shines@cs.fsu.edu * this software without specific prior written permission. 156019Shines@cs.fsu.edu * 166019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * Authors: Nathan Binkert 296019Shines@cs.fsu.edu */ 306019Shines@cs.fsu.edu 316019Shines@cs.fsu.edu#include <errno.h> 326019Shines@cs.fsu.edu#include <fcntl.h> 336019Shines@cs.fsu.edu#include <unistd.h> 346019Shines@cs.fsu.edu 356019Shines@cs.fsu.edu#include <string> 366019Shines@cs.fsu.edu 376019Shines@cs.fsu.edu#include "sim/pseudo_inst.hh" 386019Shines@cs.fsu.edu#include "arch/vtophys.hh" 396019Shines@cs.fsu.edu#include "cpu/base.hh" 407399SAli.Saidi@ARM.com#include "cpu/sampler/sampler.hh" 417399SAli.Saidi@ARM.com#include "cpu/thread_context.hh" 426019Shines@cs.fsu.edu#include "cpu/quiesce_event.hh" 436019Shines@cs.fsu.edu#include "kern/kernel_stats.hh" 446019Shines@cs.fsu.edu#include "sim/param.hh" 4510873Sandreas.sandberg@arm.com#include "sim/serialize.hh" 4610873Sandreas.sandberg@arm.com#include "sim/sim_exit.hh" 4710474Sandreas.hansson@arm.com#include "sim/stat_control.hh" 486019Shines@cs.fsu.edu#include "sim/stats.hh" 496019Shines@cs.fsu.edu#include "sim/system.hh" 506019Shines@cs.fsu.edu#include "sim/debug.hh" 516116Snate@binkert.org#include "sim/vptr.hh" 526019Shines@cs.fsu.edu 538782Sgblack@eecs.umich.eduusing namespace std; 548756Sgblack@eecs.umich.edu 5510037SARM gem5 Developersextern Sampler *SampCPU; 5610037SARM gem5 Developers 576019Shines@cs.fsu.eduusing namespace Stats; 586019Shines@cs.fsu.eduusing namespace TheISA; 596019Shines@cs.fsu.edu 606019Shines@cs.fsu.edunamespace AlphaPseudo 6110024Sdam.sunwoo@arm.com{ 626019Shines@cs.fsu.edu bool doStatisticsInsts; 638232Snate@binkert.org bool doCheckpointInsts; 648232Snate@binkert.org bool doQuiesce; 658232Snate@binkert.org 666116Snate@binkert.org void 676116Snate@binkert.org arm(ThreadContext *tc) 688756Sgblack@eecs.umich.edu { 696019Shines@cs.fsu.edu if (tc->getKernelStats()) 706019Shines@cs.fsu.edu tc->getKernelStats()->arm(); 716019Shines@cs.fsu.edu } 726019Shines@cs.fsu.edu 736019Shines@cs.fsu.edu void 7410037SARM gem5 Developers quiesce(ThreadContext *tc) 7510037SARM gem5 Developers { 7610418Sandreas.hansson@arm.com if (!doQuiesce) 7710418Sandreas.hansson@arm.com return; 7811395Sandreas.sandberg@arm.com 7910537Sandreas.hansson@arm.com tc->suspend(); 8010537Sandreas.hansson@arm.com if (tc->getKernelStats()) 8111152Smitch.hayenga@arm.com tc->getKernelStats()->quiesce(); 826019Shines@cs.fsu.edu } 8310037SARM gem5 Developers 847399SAli.Saidi@ARM.com void 8510037SARM gem5 Developers quiesceNs(ThreadContext *tc, uint64_t ns) 8610037SARM gem5 Developers { 8710037SARM gem5 Developers if (!doQuiesce || ns == 0) 8810037SARM gem5 Developers return; 896019Shines@cs.fsu.edu 906019Shines@cs.fsu.edu EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent(); 916019Shines@cs.fsu.edu 926019Shines@cs.fsu.edu if (quiesceEvent->scheduled()) 9310037SARM gem5 Developers quiesceEvent->reschedule(curTick + Clock::Int::ns * ns); 9410037SARM gem5 Developers else 9510037SARM gem5 Developers quiesceEvent->schedule(curTick + Clock::Int::ns * ns); 9610037SARM gem5 Developers 9710037SARM gem5 Developers tc->suspend(); 9810037SARM gem5 Developers if (tc->getKernelStats()) 9910037SARM gem5 Developers tc->getKernelStats()->quiesce(); 10010037SARM gem5 Developers } 10110037SARM gem5 Developers 10210037SARM gem5 Developers void 10310037SARM gem5 Developers quiesceCycles(ThreadContext *tc, uint64_t cycles) 10410717Sandreas.hansson@arm.com { 10510037SARM gem5 Developers if (!doQuiesce || cycles == 0) 10610037SARM gem5 Developers return; 10710717Sandreas.hansson@arm.com 1086019Shines@cs.fsu.edu EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent(); 1096019Shines@cs.fsu.edu 1107694SAli.Saidi@ARM.com if (quiesceEvent->scheduled()) 1117694SAli.Saidi@ARM.com quiesceEvent->reschedule(curTick + 1127694SAli.Saidi@ARM.com tc->getCpuPtr()->cycles(cycles)); 11310037SARM gem5 Developers else 11410037SARM gem5 Developers quiesceEvent->schedule(curTick + 11510037SARM gem5 Developers tc->getCpuPtr()->cycles(cycles)); 11610037SARM gem5 Developers 11710037SARM gem5 Developers tc->suspend(); 11810037SARM gem5 Developers if (tc->getKernelStats()) 11910037SARM gem5 Developers tc->getKernelStats()->quiesce(); 12010037SARM gem5 Developers } 12110037SARM gem5 Developers 1227694SAli.Saidi@ARM.com uint64_t 1237694SAli.Saidi@ARM.com quiesceTime(ThreadContext *tc) 1247694SAli.Saidi@ARM.com { 1257694SAli.Saidi@ARM.com return (tc->readLastActivate() - tc->readLastSuspend()) / Clock::Int::ns; 1267694SAli.Saidi@ARM.com } 1277694SAli.Saidi@ARM.com 1289738Sandreas@sandberg.pp.se void 1299738Sandreas@sandberg.pp.se ivlb(ThreadContext *tc) 1309738Sandreas@sandberg.pp.se { 1319738Sandreas@sandberg.pp.se if (tc->getKernelStats()) 1329738Sandreas@sandberg.pp.se tc->getKernelStats()->ivlb(); 1339738Sandreas@sandberg.pp.se } 1347404SAli.Saidi@ARM.com 13510037SARM gem5 Developers void 13610037SARM gem5 Developers ivle(ThreadContext *tc) 1376019Shines@cs.fsu.edu { 1387404SAli.Saidi@ARM.com } 1397404SAli.Saidi@ARM.com 1407404SAli.Saidi@ARM.com void 14110037SARM gem5 Developers m5exit_old(ThreadContext *tc) 1427404SAli.Saidi@ARM.com { 1437404SAli.Saidi@ARM.com exitSimLoop(curTick, "m5_exit_old instruction encountered"); 14410037SARM gem5 Developers } 14510037SARM gem5 Developers 14610037SARM gem5 Developers void 14710037SARM gem5 Developers m5exit(ThreadContext *tc, Tick delay) 14810037SARM gem5 Developers { 1499535Smrinmoy.ghosh@arm.com Tick when = curTick + delay * Clock::Int::ns; 1507697SAli.Saidi@ARM.com exitSimLoop(when, "m5_exit instruction encountered"); 15111321Ssteve.reinhardt@amd.com } 15210037SARM gem5 Developers 1537697SAli.Saidi@ARM.com void 1547697SAli.Saidi@ARM.com resetstats(ThreadContext *tc, Tick delay, Tick period) 1557697SAli.Saidi@ARM.com { 1567697SAli.Saidi@ARM.com if (!doStatisticsInsts) 1577697SAli.Saidi@ARM.com return; 1587404SAli.Saidi@ARM.com 1597404SAli.Saidi@ARM.com 16010037SARM gem5 Developers Tick when = curTick + delay * Clock::Int::ns; 1617404SAli.Saidi@ARM.com Tick repeat = period * Clock::Int::ns; 1627404SAli.Saidi@ARM.com 16310037SARM gem5 Developers using namespace Stats; 16410037SARM gem5 Developers SetupEvent(Reset, when, repeat); 16510037SARM gem5 Developers } 16610037SARM gem5 Developers 16710037SARM gem5 Developers void 16810037SARM gem5 Developers dumpstats(ThreadContext *tc, Tick delay, Tick period) 16910037SARM gem5 Developers { 17010037SARM gem5 Developers if (!doStatisticsInsts) 17110367SAndrew.Bardsley@arm.com return; 17210037SARM gem5 Developers 1737404SAli.Saidi@ARM.com 1746019Shines@cs.fsu.edu Tick when = curTick + delay * Clock::Int::ns; 1756019Shines@cs.fsu.edu Tick repeat = period * Clock::Int::ns; 1766019Shines@cs.fsu.edu 1776019Shines@cs.fsu.edu using namespace Stats; 1787404SAli.Saidi@ARM.com SetupEvent(Dump, when, repeat); 1796019Shines@cs.fsu.edu } 1807404SAli.Saidi@ARM.com 18110037SARM gem5 Developers void 18210037SARM gem5 Developers addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr) 18310037SARM gem5 Developers { 18410037SARM gem5 Developers char symb[100]; 18510037SARM gem5 Developers CopyStringOut(tc, symb, symbolAddr, 100); 18610037SARM gem5 Developers std::string symbol(symb); 1877404SAli.Saidi@ARM.com 18810037SARM gem5 Developers DPRINTF(Loader, "Loaded symbol: %s @ %#llx\n", symbol, addr); 18910037SARM gem5 Developers 19010037SARM gem5 Developers tc->getSystemPtr()->kernelSymtab->insert(addr,symbol); 1917697SAli.Saidi@ARM.com } 19210037SARM gem5 Developers 19310037SARM gem5 Developers void 19410037SARM gem5 Developers dumpresetstats(ThreadContext *tc, Tick delay, Tick period) 19510037SARM gem5 Developers { 1967404SAli.Saidi@ARM.com if (!doStatisticsInsts) 1977697SAli.Saidi@ARM.com return; 1987404SAli.Saidi@ARM.com 19910037SARM gem5 Developers 20010037SARM gem5 Developers Tick when = curTick + delay * Clock::Int::ns; 2017697SAli.Saidi@ARM.com Tick repeat = period * Clock::Int::ns; 2027734SAli.Saidi@ARM.com 2037734SAli.Saidi@ARM.com using namespace Stats; 20410463SAndreas.Sandberg@ARM.com SetupEvent(Dump|Reset, when, repeat); 2056019Shines@cs.fsu.edu } 2066019Shines@cs.fsu.edu 2076019Shines@cs.fsu.edu void 20810037SARM gem5 Developers m5checkpoint(ThreadContext *tc, Tick delay, Tick period) 2097404SAli.Saidi@ARM.com { 2107404SAli.Saidi@ARM.com if (!doCheckpointInsts) 2117404SAli.Saidi@ARM.com return; 2127404SAli.Saidi@ARM.com } 2137404SAli.Saidi@ARM.com 21410037SARM gem5 Developers uint64_t 21510037SARM gem5 Developers readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset) 21610037SARM gem5 Developers { 21710037SARM gem5 Developers const string &file = tc->getCpuPtr()->system->params()->readfile; 2187404SAli.Saidi@ARM.com if (file.empty()) { 2197404SAli.Saidi@ARM.com return ULL(0); 2207404SAli.Saidi@ARM.com } 2217404SAli.Saidi@ARM.com 22210037SARM gem5 Developers uint64_t result = 0; 2236019Shines@cs.fsu.edu 22410037SARM gem5 Developers int fd = ::open(file.c_str(), O_RDONLY, 0); 22510037SARM gem5 Developers if (fd < 0) 2267404SAli.Saidi@ARM.com panic("could not open file %s\n", file); 2277404SAli.Saidi@ARM.com 2287404SAli.Saidi@ARM.com if (::lseek(fd, offset, SEEK_SET) < 0) 22910037SARM gem5 Developers panic("could not seek: %s", strerror(errno)); 23010037SARM gem5 Developers 23110037SARM gem5 Developers char *buf = new char[len]; 23210037SARM gem5 Developers char *p = buf; 23310037SARM gem5 Developers while (len > 0) { 23410037SARM gem5 Developers int bytes = ::read(fd, p, len); 23510037SARM gem5 Developers if (bytes <= 0) 23610037SARM gem5 Developers break; 23710037SARM gem5 Developers 23810037SARM gem5 Developers p += bytes; 2397404SAli.Saidi@ARM.com result += bytes; 2407404SAli.Saidi@ARM.com len -= bytes; 24110037SARM gem5 Developers } 24210037SARM gem5 Developers 24310037SARM gem5 Developers close(fd); 24410037SARM gem5 Developers CopyIn(tc, vaddr, buf, result); 24510037SARM gem5 Developers delete [] buf; 24610037SARM gem5 Developers return result; 24710037SARM gem5 Developers } 24810037SARM gem5 Developers 24910037SARM gem5 Developers class Context : public ParamContext 25010037SARM gem5 Developers { 25110037SARM gem5 Developers public: 25210037SARM gem5 Developers Context(const string §ion) : ParamContext(section) {} 25310037SARM gem5 Developers void checkParams(); 25410037SARM gem5 Developers }; 25510037SARM gem5 Developers 25610037SARM gem5 Developers Context context("pseudo_inst"); 25710037SARM gem5 Developers 25810037SARM gem5 Developers Param<bool> __quiesce(&context, "quiesce", 25910037SARM gem5 Developers "enable quiesce instructions", 26010037SARM gem5 Developers true); 26110037SARM gem5 Developers Param<bool> __statistics(&context, "statistics", 26210037SARM gem5 Developers "enable statistics pseudo instructions", 26310037SARM gem5 Developers true); 26410037SARM gem5 Developers Param<bool> __checkpoint(&context, "checkpoint", 26510037SARM gem5 Developers "enable checkpoint pseudo instructions", 26610037SARM gem5 Developers true); 26710037SARM gem5 Developers 2687734SAli.Saidi@ARM.com void 2697734SAli.Saidi@ARM.com Context::checkParams() 27010037SARM gem5 Developers { 27110037SARM gem5 Developers doQuiesce = __quiesce; 27210037SARM gem5 Developers doStatisticsInsts = __statistics; 27310037SARM gem5 Developers doCheckpointInsts = __checkpoint; 27410037SARM gem5 Developers } 2756019Shines@cs.fsu.edu 2766019Shines@cs.fsu.edu void debugbreak(ThreadContext *tc) 2777404SAli.Saidi@ARM.com { 27810037SARM gem5 Developers debug_break(); 2797404SAli.Saidi@ARM.com } 28010037SARM gem5 Developers 28110037SARM gem5 Developers void switchcpu(ThreadContext *tc) 28210037SARM gem5 Developers { 28310037SARM gem5 Developers if (SampCPU) 2847734SAli.Saidi@ARM.com SampCPU->switchCPUs(); 2857404SAli.Saidi@ARM.com } 2867404SAli.Saidi@ARM.com} 2877404SAli.Saidi@ARM.com