pseudo_inst.cc revision 11270:a3b41de1c4f1
16019Shines@cs.fsu.edu/* 26019Shines@cs.fsu.edu * Copyright (c) 2010-2012, 2015 ARM Limited 36019Shines@cs.fsu.edu * All rights reserved 46019Shines@cs.fsu.edu * 56019Shines@cs.fsu.edu * The license below extends only to copyright in the software and shall 66019Shines@cs.fsu.edu * not be construed as granting a license to any other intellectual 76019Shines@cs.fsu.edu * property including but not limited to intellectual property relating 86019Shines@cs.fsu.edu * to a hardware implementation of the functionality of the software 96019Shines@cs.fsu.edu * licensed hereunder. You may use the software subject to the license 106019Shines@cs.fsu.edu * terms below provided that you ensure that this notice is replicated 116019Shines@cs.fsu.edu * unmodified and in its entirety in all distributions of the software, 126019Shines@cs.fsu.edu * modified or unmodified, in source code or in binary form. 136019Shines@cs.fsu.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2011 Advanced Micro Devices, Inc. 156019Shines@cs.fsu.edu * Copyright (c) 2003-2006 The Regents of The University of Michigan 166019Shines@cs.fsu.edu * All rights reserved. 176019Shines@cs.fsu.edu * 186019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 196019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 206019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 216019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 226019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 236019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 246019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 256019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 266019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 276019Shines@cs.fsu.edu * this software without specific prior written permission. 286019Shines@cs.fsu.edu * 296019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326020Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396116Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019Shines@cs.fsu.edu * 416019Shines@cs.fsu.edu * Authors: Nathan Binkert 426019Shines@cs.fsu.edu */ 436019Shines@cs.fsu.edu 446019Shines@cs.fsu.edu#include <fcntl.h> 456019Shines@cs.fsu.edu#include <unistd.h> 466019Shines@cs.fsu.edu 476116Snate@binkert.org#include <cerrno> 486116Snate@binkert.org#include <fstream> 496019Shines@cs.fsu.edu#include <string> 506019Shines@cs.fsu.edu#include <vector> 516019Shines@cs.fsu.edu 526019Shines@cs.fsu.edu#include "arch/kernel_stats.hh" 536019Shines@cs.fsu.edu#include "arch/utility.hh" 546019Shines@cs.fsu.edu#include "arch/vtophys.hh" 556019Shines@cs.fsu.edu#include "arch/pseudo_inst.hh" 566019Shines@cs.fsu.edu#include "base/debug.hh" 576019Shines@cs.fsu.edu#include "base/output.hh" 586019Shines@cs.fsu.edu#include "config/the_isa.hh" 596019Shines@cs.fsu.edu#include "cpu/base.hh" 606019Shines@cs.fsu.edu#include "cpu/quiesce_event.hh" 616019Shines@cs.fsu.edu#include "cpu/thread_context.hh" 626019Shines@cs.fsu.edu#include "debug/Loader.hh" 636019Shines@cs.fsu.edu#include "debug/PseudoInst.hh" 646019Shines@cs.fsu.edu#include "debug/Quiesce.hh" 656019Shines@cs.fsu.edu#include "debug/WorkItems.hh" 666019Shines@cs.fsu.edu#include "params/BaseCPU.hh" 676019Shines@cs.fsu.edu#include "sim/full_system.hh" 686019Shines@cs.fsu.edu#include "sim/process.hh" 696019Shines@cs.fsu.edu#include "sim/pseudo_inst.hh" 706019Shines@cs.fsu.edu#include "sim/serialize.hh" 716019Shines@cs.fsu.edu#include "sim/sim_events.hh" 726019Shines@cs.fsu.edu#include "sim/sim_exit.hh" 736019Shines@cs.fsu.edu#include "sim/stat_control.hh" 746019Shines@cs.fsu.edu#include "sim/stats.hh" 756019Shines@cs.fsu.edu#include "sim/system.hh" 766019Shines@cs.fsu.edu#include "sim/vptr.hh" 776019Shines@cs.fsu.edu 786019Shines@cs.fsu.eduusing namespace std; 796019Shines@cs.fsu.edu 806019Shines@cs.fsu.eduusing namespace Stats; 816019Shines@cs.fsu.eduusing namespace TheISA; 826019Shines@cs.fsu.edu 836019Shines@cs.fsu.edunamespace PseudoInst { 846019Shines@cs.fsu.edu 856019Shines@cs.fsu.edustatic inline void 866019Shines@cs.fsu.edupanicFsOnlyPseudoInst(const char *name) 876019Shines@cs.fsu.edu{ 886019Shines@cs.fsu.edu panic("Pseudo inst \"%s\" is only available in Full System mode."); 896019Shines@cs.fsu.edu} 906019Shines@cs.fsu.edu 916019Shines@cs.fsu.eduuint64_t 926019Shines@cs.fsu.edupseudoInst(ThreadContext *tc, uint8_t func, uint8_t subfunc) 936019Shines@cs.fsu.edu{ 946019Shines@cs.fsu.edu uint64_t args[4]; 956019Shines@cs.fsu.edu 966019Shines@cs.fsu.edu DPRINTF(PseudoInst, "PseudoInst::pseudoInst(%i, %i)\n", func, subfunc); 976019Shines@cs.fsu.edu 986019Shines@cs.fsu.edu // We need to do this in a slightly convoluted way since 996019Shines@cs.fsu.edu // getArgument() might have side-effects on arg_num. We could have 1006019Shines@cs.fsu.edu // used the Argument class, but due to the possible side effects 1016019Shines@cs.fsu.edu // from getArgument, it'd most likely break. 1026019Shines@cs.fsu.edu int arg_num(0); 1036019Shines@cs.fsu.edu for (int i = 0; i < sizeof(args) / sizeof(*args); ++i) { 1046019Shines@cs.fsu.edu args[arg_num] = getArgument(tc, arg_num, sizeof(uint64_t), false); 1056019Shines@cs.fsu.edu ++arg_num; 1066019Shines@cs.fsu.edu } 1076019Shines@cs.fsu.edu 1086019Shines@cs.fsu.edu switch (func) { 1096019Shines@cs.fsu.edu case 0x00: // arm_func 1106019Shines@cs.fsu.edu arm(tc); 1116019Shines@cs.fsu.edu break; 1126019Shines@cs.fsu.edu 1136019Shines@cs.fsu.edu case 0x01: // quiesce_func 1146019Shines@cs.fsu.edu quiesce(tc); 1156019Shines@cs.fsu.edu break; 1166019Shines@cs.fsu.edu 1176019Shines@cs.fsu.edu case 0x02: // quiescens_func 1186019Shines@cs.fsu.edu quiesceSkip(tc); 1196019Shines@cs.fsu.edu break; 1206019Shines@cs.fsu.edu 1216019Shines@cs.fsu.edu case 0x03: // quiescecycle_func 1226019Shines@cs.fsu.edu quiesceNs(tc, args[0]); 1236019Shines@cs.fsu.edu break; 1246019Shines@cs.fsu.edu 1256019Shines@cs.fsu.edu case 0x04: // quiescetime_func 1266019Shines@cs.fsu.edu return quiesceTime(tc); 1276019Shines@cs.fsu.edu 1286019Shines@cs.fsu.edu case 0x07: // rpns_func 1296019Shines@cs.fsu.edu return rpns(tc); 1306019Shines@cs.fsu.edu 1316019Shines@cs.fsu.edu case 0x09: // wakecpu_func 1326019Shines@cs.fsu.edu wakeCPU(tc, args[0]); 1336019Shines@cs.fsu.edu break; 1346019Shines@cs.fsu.edu 1356019Shines@cs.fsu.edu case 0x21: // exit_func 1366019Shines@cs.fsu.edu m5exit(tc, args[0]); 1376019Shines@cs.fsu.edu break; 1386019Shines@cs.fsu.edu 1396019Shines@cs.fsu.edu case 0x22: 1406019Shines@cs.fsu.edu m5fail(tc, args[0], args[1]); 1416019Shines@cs.fsu.edu break; 1426019Shines@cs.fsu.edu 1436019Shines@cs.fsu.edu case 0x30: // initparam_func 1446019Shines@cs.fsu.edu return initParam(tc); 1456019Shines@cs.fsu.edu 1466019Shines@cs.fsu.edu case 0x31: // loadsymbol_func 1476019Shines@cs.fsu.edu loadsymbol(tc); 1486019Shines@cs.fsu.edu break; 1496019Shines@cs.fsu.edu 1506428Ssteve.reinhardt@amd.com case 0x40: // resetstats_func 1516019Shines@cs.fsu.edu resetstats(tc, args[0], args[1]); 1526019Shines@cs.fsu.edu break; 1536019Shines@cs.fsu.edu 1546019Shines@cs.fsu.edu case 0x41: // dumpstats_func 1556019Shines@cs.fsu.edu dumpstats(tc, args[0], args[1]); 1566019Shines@cs.fsu.edu break; 1576019Shines@cs.fsu.edu 1586019Shines@cs.fsu.edu case 0x42: // dumprststats_func 1596019Shines@cs.fsu.edu dumpresetstats(tc, args[0], args[1]); 1606019Shines@cs.fsu.edu break; 1616019Shines@cs.fsu.edu 1626019Shines@cs.fsu.edu case 0x43: // ckpt_func 1636019Shines@cs.fsu.edu m5checkpoint(tc, args[0], args[1]); 1646019Shines@cs.fsu.edu break; 1656019Shines@cs.fsu.edu 1666019Shines@cs.fsu.edu case 0x4f: // writefile_func 1676019Shines@cs.fsu.edu return writefile(tc, args[0], args[1], args[2], args[3]); 1686019Shines@cs.fsu.edu 1696019Shines@cs.fsu.edu case 0x50: // readfile_func 1706019Shines@cs.fsu.edu return readfile(tc, args[0], args[1], args[2]); 1716019Shines@cs.fsu.edu 1726019Shines@cs.fsu.edu case 0x51: // debugbreak_func 1736019Shines@cs.fsu.edu debugbreak(tc); 1746019Shines@cs.fsu.edu break; 1756019Shines@cs.fsu.edu 1766019Shines@cs.fsu.edu case 0x52: // switchcpu_func 1776019Shines@cs.fsu.edu switchcpu(tc); 1786019Shines@cs.fsu.edu break; 1796019Shines@cs.fsu.edu 1806019Shines@cs.fsu.edu case 0x53: // addsymbol_func 1816019Shines@cs.fsu.edu addsymbol(tc, args[0], args[1]); 1826019Shines@cs.fsu.edu break; 1836019Shines@cs.fsu.edu 1846019Shines@cs.fsu.edu case 0x54: // panic_func 1856019Shines@cs.fsu.edu panic("M5 panic instruction called at %s\n", tc->pcState()); 1866019Shines@cs.fsu.edu 1876019Shines@cs.fsu.edu case 0x5a: // work_begin_func 1886019Shines@cs.fsu.edu workbegin(tc, args[0], args[1]); 1896019Shines@cs.fsu.edu break; 1906019Shines@cs.fsu.edu 1916019Shines@cs.fsu.edu case 0x5b: // work_end_func 1926019Shines@cs.fsu.edu workend(tc, args[0], args[1]); 1936019Shines@cs.fsu.edu break; 1946019Shines@cs.fsu.edu 1956019Shines@cs.fsu.edu case 0x55: // annotate_func 1966019Shines@cs.fsu.edu case 0x56: // reserved2_func 1976019Shines@cs.fsu.edu case 0x57: // reserved3_func 1986019Shines@cs.fsu.edu case 0x58: // reserved4_func 1996019Shines@cs.fsu.edu case 0x59: // reserved5_func 2006019Shines@cs.fsu.edu warn("Unimplemented m5 op (0x%x)\n", func); 2016019Shines@cs.fsu.edu break; 2026019Shines@cs.fsu.edu 2036019Shines@cs.fsu.edu /* SE mode functions */ 2046019Shines@cs.fsu.edu case 0x60: // syscall_func 2056019Shines@cs.fsu.edu m5Syscall(tc); 2066019Shines@cs.fsu.edu break; 2076019Shines@cs.fsu.edu 2086019Shines@cs.fsu.edu case 0x61: // pagefault_func 2096019Shines@cs.fsu.edu m5PageFault(tc); 2106019Shines@cs.fsu.edu break; 2116019Shines@cs.fsu.edu 2126019Shines@cs.fsu.edu default: 2136019Shines@cs.fsu.edu warn("Unhandled m5 op: 0x%x\n", func); 2146019Shines@cs.fsu.edu break; 2156019Shines@cs.fsu.edu } 2166019Shines@cs.fsu.edu 2176019Shines@cs.fsu.edu return 0; 2186019Shines@cs.fsu.edu} 2196019Shines@cs.fsu.edu 2206019Shines@cs.fsu.eduvoid 2216019Shines@cs.fsu.eduarm(ThreadContext *tc) 2226019Shines@cs.fsu.edu{ 2236019Shines@cs.fsu.edu DPRINTF(PseudoInst, "PseudoInst::arm()\n"); 2246019Shines@cs.fsu.edu if (!FullSystem) 2256019Shines@cs.fsu.edu panicFsOnlyPseudoInst("arm"); 2266019Shines@cs.fsu.edu 2276019Shines@cs.fsu.edu if (tc->getKernelStats()) 2286019Shines@cs.fsu.edu tc->getKernelStats()->arm(); 2296019Shines@cs.fsu.edu} 2306019Shines@cs.fsu.edu 2316019Shines@cs.fsu.eduvoid 2326019Shines@cs.fsu.eduquiesce(ThreadContext *tc) 2336019Shines@cs.fsu.edu{ 2346019Shines@cs.fsu.edu DPRINTF(PseudoInst, "PseudoInst::quiesce()\n"); 2356019Shines@cs.fsu.edu if (!FullSystem) 2366019Shines@cs.fsu.edu panicFsOnlyPseudoInst("quiesce"); 2376019Shines@cs.fsu.edu 2386019Shines@cs.fsu.edu if (!tc->getCpuPtr()->params()->do_quiesce) 2396019Shines@cs.fsu.edu return; 2406019Shines@cs.fsu.edu 2416019Shines@cs.fsu.edu DPRINTF(Quiesce, "%s: quiesce()\n", tc->getCpuPtr()->name()); 2426019Shines@cs.fsu.edu 2436019Shines@cs.fsu.edu tc->suspend(); 2446019Shines@cs.fsu.edu if (tc->getKernelStats()) 2456019Shines@cs.fsu.edu tc->getKernelStats()->quiesce(); 2466019Shines@cs.fsu.edu} 2476019Shines@cs.fsu.edu 2486019Shines@cs.fsu.eduvoid 2496019Shines@cs.fsu.eduquiesceSkip(ThreadContext *tc) 2506019Shines@cs.fsu.edu{ 2516019Shines@cs.fsu.edu DPRINTF(PseudoInst, "PseudoInst::quiesceSkip()\n"); 2526019Shines@cs.fsu.edu if (!FullSystem) 2536019Shines@cs.fsu.edu panicFsOnlyPseudoInst("quiesceSkip"); 2546019Shines@cs.fsu.edu 2556019Shines@cs.fsu.edu BaseCPU *cpu = tc->getCpuPtr(); 2566019Shines@cs.fsu.edu 2576019Shines@cs.fsu.edu if (!cpu->params()->do_quiesce) 2586019Shines@cs.fsu.edu return; 2596019Shines@cs.fsu.edu 2606019Shines@cs.fsu.edu EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent(); 2616019Shines@cs.fsu.edu 2626019Shines@cs.fsu.edu Tick resume = curTick() + 1; 2636019Shines@cs.fsu.edu 2646019Shines@cs.fsu.edu cpu->reschedule(quiesceEvent, resume, true); 2656019Shines@cs.fsu.edu 2666019Shines@cs.fsu.edu DPRINTF(Quiesce, "%s: quiesceSkip() until %d\n", 2676019Shines@cs.fsu.edu cpu->name(), resume); 2686019Shines@cs.fsu.edu 2696019Shines@cs.fsu.edu tc->suspend(); 2706019Shines@cs.fsu.edu if (tc->getKernelStats()) 2716019Shines@cs.fsu.edu tc->getKernelStats()->quiesce(); 2726019Shines@cs.fsu.edu} 2736019Shines@cs.fsu.edu 2746019Shines@cs.fsu.eduvoid 2756019Shines@cs.fsu.eduquiesceNs(ThreadContext *tc, uint64_t ns) 2766019Shines@cs.fsu.edu{ 2776019Shines@cs.fsu.edu DPRINTF(PseudoInst, "PseudoInst::quiesceNs(%i)\n", ns); 2786019Shines@cs.fsu.edu if (!FullSystem) 2796116Snate@binkert.org panicFsOnlyPseudoInst("quiesceNs"); 2806019Shines@cs.fsu.edu 2816019Shines@cs.fsu.edu BaseCPU *cpu = tc->getCpuPtr(); 2826019Shines@cs.fsu.edu 2836019Shines@cs.fsu.edu if (!cpu->params()->do_quiesce) 2846019Shines@cs.fsu.edu return; 2856019Shines@cs.fsu.edu 2866019Shines@cs.fsu.edu EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent(); 2876019Shines@cs.fsu.edu 2886019Shines@cs.fsu.edu Tick resume = curTick() + SimClock::Int::ns * ns; 2896019Shines@cs.fsu.edu 2906757SAli.Saidi@ARM.com cpu->reschedule(quiesceEvent, resume, true); 2916757SAli.Saidi@ARM.com 2926757SAli.Saidi@ARM.com DPRINTF(Quiesce, "%s: quiesceNs(%d) until %d\n", 2936757SAli.Saidi@ARM.com cpu->name(), ns, resume); 2946757SAli.Saidi@ARM.com 2956757SAli.Saidi@ARM.com tc->suspend(); 2966757SAli.Saidi@ARM.com if (tc->getKernelStats()) 2976757SAli.Saidi@ARM.com tc->getKernelStats()->quiesce(); 2986757SAli.Saidi@ARM.com} 2996019Shines@cs.fsu.edu 3006019Shines@cs.fsu.eduvoid 3016019Shines@cs.fsu.eduquiesceCycles(ThreadContext *tc, uint64_t cycles) 3026020Sgblack@eecs.umich.edu{ 3036116Snate@binkert.org DPRINTF(PseudoInst, "PseudoInst::quiesceCycles(%i)\n", cycles); 3046116Snate@binkert.org if (!FullSystem) 3056020Sgblack@eecs.umich.edu panicFsOnlyPseudoInst("quiesceCycles"); 3066020Sgblack@eecs.umich.edu 3076116Snate@binkert.org BaseCPU *cpu = tc->getCpuPtr(); 3086020Sgblack@eecs.umich.edu 3096020Sgblack@eecs.umich.edu if (!cpu->params()->do_quiesce) 3106019Shines@cs.fsu.edu return; 3116019Shines@cs.fsu.edu 3126019Shines@cs.fsu.edu EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent(); 3136019Shines@cs.fsu.edu 3146019Shines@cs.fsu.edu Tick resume = cpu->clockEdge(Cycles(cycles)); 3156019Shines@cs.fsu.edu 3166019Shines@cs.fsu.edu cpu->reschedule(quiesceEvent, resume, true); 3176019Shines@cs.fsu.edu 3186019Shines@cs.fsu.edu DPRINTF(Quiesce, "%s: quiesceCycles(%d) until %d\n", 3196019Shines@cs.fsu.edu cpu->name(), cycles, resume); 3206019Shines@cs.fsu.edu 3216116Snate@binkert.org tc->suspend(); 3226116Snate@binkert.org if (tc->getKernelStats()) 3236019Shines@cs.fsu.edu tc->getKernelStats()->quiesce(); 3246116Snate@binkert.org} 3256019Shines@cs.fsu.edu 326uint64_t 327quiesceTime(ThreadContext *tc) 328{ 329 DPRINTF(PseudoInst, "PseudoInst::quiesceTime()\n"); 330 if (!FullSystem) { 331 panicFsOnlyPseudoInst("quiesceTime"); 332 return 0; 333 } 334 335 return (tc->readLastActivate() - tc->readLastSuspend()) / 336 SimClock::Int::ns; 337} 338 339uint64_t 340rpns(ThreadContext *tc) 341{ 342 DPRINTF(PseudoInst, "PseudoInst::rpns()\n"); 343 return curTick() / SimClock::Int::ns; 344} 345 346void 347wakeCPU(ThreadContext *tc, uint64_t cpuid) 348{ 349 DPRINTF(PseudoInst, "PseudoInst::wakeCPU(%i)\n", cpuid); 350 System *sys = tc->getSystemPtr(); 351 ThreadContext *other_tc = sys->threadContexts[cpuid]; 352 if (other_tc->status() == ThreadContext::Suspended) 353 other_tc->activate(); 354} 355 356void 357m5exit(ThreadContext *tc, Tick delay) 358{ 359 DPRINTF(PseudoInst, "PseudoInst::m5exit(%i)\n", delay); 360 Tick when = curTick() + delay * SimClock::Int::ns; 361 exitSimLoop("m5_exit instruction encountered", 0, when, 0, true); 362} 363 364void 365m5fail(ThreadContext *tc, Tick delay, uint64_t code) 366{ 367 DPRINTF(PseudoInst, "PseudoInst::m5fail(%i, %i)\n", delay, code); 368 Tick when = curTick() + delay * SimClock::Int::ns; 369 exitSimLoop("m5_fail instruction encountered", code, when, 0, true); 370} 371 372void 373loadsymbol(ThreadContext *tc) 374{ 375 DPRINTF(PseudoInst, "PseudoInst::loadsymbol()\n"); 376 if (!FullSystem) 377 panicFsOnlyPseudoInst("loadsymbol"); 378 379 const string &filename = tc->getCpuPtr()->system->params()->symbolfile; 380 if (filename.empty()) { 381 return; 382 } 383 384 std::string buffer; 385 ifstream file(filename.c_str()); 386 387 if (!file) 388 fatal("file error: Can't open symbol table file %s\n", filename); 389 390 while (!file.eof()) { 391 getline(file, buffer); 392 393 if (buffer.empty()) 394 continue; 395 396 string::size_type idx = buffer.find(' '); 397 if (idx == string::npos) 398 continue; 399 400 string address = "0x" + buffer.substr(0, idx); 401 eat_white(address); 402 if (address.empty()) 403 continue; 404 405 // Skip over letter and space 406 string symbol = buffer.substr(idx + 3); 407 eat_white(symbol); 408 if (symbol.empty()) 409 continue; 410 411 Addr addr; 412 if (!to_number(address, addr)) 413 continue; 414 415 if (!tc->getSystemPtr()->kernelSymtab->insert(addr, symbol)) 416 continue; 417 418 419 DPRINTF(Loader, "Loaded symbol: %s @ %#llx\n", symbol, addr); 420 } 421 file.close(); 422} 423 424void 425addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr) 426{ 427 DPRINTF(PseudoInst, "PseudoInst::addsymbol(0x%x, 0x%x)\n", 428 addr, symbolAddr); 429 if (!FullSystem) 430 panicFsOnlyPseudoInst("addSymbol"); 431 432 char symb[100]; 433 CopyStringOut(tc, symb, symbolAddr, 100); 434 std::string symbol(symb); 435 436 DPRINTF(Loader, "Loaded symbol: %s @ %#llx\n", symbol, addr); 437 438 tc->getSystemPtr()->kernelSymtab->insert(addr,symbol); 439 debugSymbolTable->insert(addr,symbol); 440} 441 442uint64_t 443initParam(ThreadContext *tc) 444{ 445 DPRINTF(PseudoInst, "PseudoInst::initParam()\n"); 446 if (!FullSystem) { 447 panicFsOnlyPseudoInst("initParam"); 448 return 0; 449 } 450 451 return tc->getCpuPtr()->system->init_param; 452} 453 454 455void 456resetstats(ThreadContext *tc, Tick delay, Tick period) 457{ 458 DPRINTF(PseudoInst, "PseudoInst::resetstats(%i, %i)\n", delay, period); 459 if (!tc->getCpuPtr()->params()->do_statistics_insts) 460 return; 461 462 463 Tick when = curTick() + delay * SimClock::Int::ns; 464 Tick repeat = period * SimClock::Int::ns; 465 466 Stats::schedStatEvent(false, true, when, repeat); 467} 468 469void 470dumpstats(ThreadContext *tc, Tick delay, Tick period) 471{ 472 DPRINTF(PseudoInst, "PseudoInst::dumpstats(%i, %i)\n", delay, period); 473 if (!tc->getCpuPtr()->params()->do_statistics_insts) 474 return; 475 476 477 Tick when = curTick() + delay * SimClock::Int::ns; 478 Tick repeat = period * SimClock::Int::ns; 479 480 Stats::schedStatEvent(true, false, when, repeat); 481} 482 483void 484dumpresetstats(ThreadContext *tc, Tick delay, Tick period) 485{ 486 DPRINTF(PseudoInst, "PseudoInst::dumpresetstats(%i, %i)\n", delay, period); 487 if (!tc->getCpuPtr()->params()->do_statistics_insts) 488 return; 489 490 491 Tick when = curTick() + delay * SimClock::Int::ns; 492 Tick repeat = period * SimClock::Int::ns; 493 494 Stats::schedStatEvent(true, true, when, repeat); 495} 496 497void 498m5checkpoint(ThreadContext *tc, Tick delay, Tick period) 499{ 500 DPRINTF(PseudoInst, "PseudoInst::m5checkpoint(%i, %i)\n", delay, period); 501 if (!tc->getCpuPtr()->params()->do_checkpoint_insts) 502 return; 503 504 Tick when = curTick() + delay * SimClock::Int::ns; 505 Tick repeat = period * SimClock::Int::ns; 506 507 exitSimLoop("checkpoint", 0, when, repeat); 508} 509 510uint64_t 511readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset) 512{ 513 DPRINTF(PseudoInst, "PseudoInst::readfile(0x%x, 0x%x, 0x%x)\n", 514 vaddr, len, offset); 515 if (!FullSystem) { 516 panicFsOnlyPseudoInst("readfile"); 517 return 0; 518 } 519 520 const string &file = tc->getSystemPtr()->params()->readfile; 521 if (file.empty()) { 522 return ULL(0); 523 } 524 525 uint64_t result = 0; 526 527 int fd = ::open(file.c_str(), O_RDONLY, 0); 528 if (fd < 0) 529 panic("could not open file %s\n", file); 530 531 if (::lseek(fd, offset, SEEK_SET) < 0) 532 panic("could not seek: %s", strerror(errno)); 533 534 char *buf = new char[len]; 535 char *p = buf; 536 while (len > 0) { 537 int bytes = ::read(fd, p, len); 538 if (bytes <= 0) 539 break; 540 541 p += bytes; 542 result += bytes; 543 len -= bytes; 544 } 545 546 close(fd); 547 CopyIn(tc, vaddr, buf, result); 548 delete [] buf; 549 return result; 550} 551 552uint64_t 553writefile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset, 554 Addr filename_addr) 555{ 556 DPRINTF(PseudoInst, "PseudoInst::writefile(0x%x, 0x%x, 0x%x, 0x%x)\n", 557 vaddr, len, offset, filename_addr); 558 ostream *os; 559 560 // copy out target filename 561 char fn[100]; 562 std::string filename; 563 CopyStringOut(tc, fn, filename_addr, 100); 564 filename = std::string(fn); 565 566 if (offset == 0) { 567 // create a new file (truncate) 568 os = simout.create(filename, true, true); 569 } else { 570 // do not truncate file if offset is non-zero 571 // (ios::in flag is required as well to keep the existing data 572 // intact, otherwise existing data will be zeroed out.) 573 os = simout.openFile(simout.directory() + filename, 574 ios::in | ios::out | ios::binary, true); 575 } 576 if (!os) 577 panic("could not open file %s\n", filename); 578 579 // seek to offset 580 os->seekp(offset); 581 582 // copy out data and write to file 583 char *buf = new char[len]; 584 CopyOut(tc, buf, vaddr, len); 585 os->write(buf, len); 586 if (os->fail() || os->bad()) 587 panic("Error while doing writefile!\n"); 588 589 simout.close(os); 590 591 delete [] buf; 592 593 return len; 594} 595 596void 597debugbreak(ThreadContext *tc) 598{ 599 DPRINTF(PseudoInst, "PseudoInst::debugbreak()\n"); 600 Debug::breakpoint(); 601} 602 603void 604switchcpu(ThreadContext *tc) 605{ 606 DPRINTF(PseudoInst, "PseudoInst::switchcpu()\n"); 607 exitSimLoop("switchcpu"); 608} 609 610// 611// This function is executed when annotated work items begin. Depending on 612// what the user specified at the command line, the simulation may exit and/or 613// take a checkpoint when a certain work item begins. 614// 615void 616workbegin(ThreadContext *tc, uint64_t workid, uint64_t threadid) 617{ 618 DPRINTF(PseudoInst, "PseudoInst::workbegin(%i, %i)\n", workid, threadid); 619 System *sys = tc->getSystemPtr(); 620 const System::Params *params = sys->params(); 621 622 if (params->exit_on_work_items) { 623 exitSimLoop("workbegin", static_cast<int>(workid)); 624 return; 625 } 626 627 DPRINTF(WorkItems, "Work Begin workid: %d, threadid %d\n", workid, 628 threadid); 629 tc->getCpuPtr()->workItemBegin(); 630 sys->workItemBegin(threadid, workid); 631 632 // 633 // If specified, determine if this is the specific work item the user 634 // identified 635 // 636 if (params->work_item_id == -1 || params->work_item_id == workid) { 637 638 uint64_t systemWorkBeginCount = sys->incWorkItemsBegin(); 639 int cpuId = tc->getCpuPtr()->cpuId(); 640 641 if (params->work_cpus_ckpt_count != 0 && 642 sys->markWorkItem(cpuId) >= params->work_cpus_ckpt_count) { 643 // 644 // If active cpus equals checkpoint count, create checkpoint 645 // 646 exitSimLoop("checkpoint"); 647 } 648 649 if (systemWorkBeginCount == params->work_begin_ckpt_count) { 650 // 651 // Note: the string specified as the cause of the exit event must 652 // exactly equal "checkpoint" inorder to create a checkpoint 653 // 654 exitSimLoop("checkpoint"); 655 } 656 657 if (systemWorkBeginCount == params->work_begin_exit_count) { 658 // 659 // If a certain number of work items started, exit simulation 660 // 661 exitSimLoop("work started count reach"); 662 } 663 664 if (cpuId == params->work_begin_cpu_id_exit) { 665 // 666 // If work started on the cpu id specified, exit simulation 667 // 668 exitSimLoop("work started on specific cpu"); 669 } 670 } 671} 672 673// 674// This function is executed when annotated work items end. Depending on 675// what the user specified at the command line, the simulation may exit and/or 676// take a checkpoint when a certain work item ends. 677// 678void 679workend(ThreadContext *tc, uint64_t workid, uint64_t threadid) 680{ 681 DPRINTF(PseudoInst, "PseudoInst::workend(%i, %i)\n", workid, threadid); 682 System *sys = tc->getSystemPtr(); 683 const System::Params *params = sys->params(); 684 685 if (params->exit_on_work_items) { 686 exitSimLoop("workend", static_cast<int>(workid)); 687 return; 688 } 689 690 DPRINTF(WorkItems, "Work End workid: %d, threadid %d\n", workid, threadid); 691 tc->getCpuPtr()->workItemEnd(); 692 sys->workItemEnd(threadid, workid); 693 694 // 695 // If specified, determine if this is the specific work item the user 696 // identified 697 // 698 if (params->work_item_id == -1 || params->work_item_id == workid) { 699 700 uint64_t systemWorkEndCount = sys->incWorkItemsEnd(); 701 int cpuId = tc->getCpuPtr()->cpuId(); 702 703 if (params->work_cpus_ckpt_count != 0 && 704 sys->markWorkItem(cpuId) >= params->work_cpus_ckpt_count) { 705 // 706 // If active cpus equals checkpoint count, create checkpoint 707 // 708 exitSimLoop("checkpoint"); 709 } 710 711 if (params->work_end_ckpt_count != 0 && 712 systemWorkEndCount == params->work_end_ckpt_count) { 713 // 714 // If total work items completed equals checkpoint count, create 715 // checkpoint 716 // 717 exitSimLoop("checkpoint"); 718 } 719 720 if (params->work_end_exit_count != 0 && 721 systemWorkEndCount == params->work_end_exit_count) { 722 // 723 // If total work items completed equals exit count, exit simulation 724 // 725 exitSimLoop("work items exit count reached"); 726 } 727 } 728} 729 730} // namespace PseudoInst 731