pseudo_inst.cc revision 1343
1298SN/A/* 28142SAli.Saidi@ARM.com * Copyright (c) 2003-2004 The Regents of The University of Michigan 38142SAli.Saidi@ARM.com * All rights reserved. 48142SAli.Saidi@ARM.com * 58142SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 68142SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 78142SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 88142SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 98142SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 108142SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 118142SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 128142SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 138142SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 148580Ssteve.reinhardt@amd.com * this software without specific prior written permission. 152188SN/A * 16298SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17298SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18298SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19298SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20298SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21298SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22298SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23298SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24298SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25298SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26298SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27298SN/A */ 28298SN/A 29298SN/A#include <fcntl.h> 30298SN/A#include <unistd.h> 31298SN/A#include <cstdio> 32298SN/A 33298SN/A#include <string> 34298SN/A 35298SN/A#include "arch/alpha/pseudo_inst.hh" 36298SN/A#include "arch/alpha/vtophys.hh" 37298SN/A#include "cpu/base_cpu.hh" 38298SN/A#include "cpu/sampling_cpu/sampling_cpu.hh" 39298SN/A#include "cpu/exec_context.hh" 402665Ssaidi@eecs.umich.edu#include "kern/kernel_stats.hh" 412665Ssaidi@eecs.umich.edu#include "sim/param.hh" 42298SN/A#include "sim/serialize.hh" 43298SN/A#include "sim/sim_exit.hh" 44954SN/A#include "sim/stat_control.hh" 45956SN/A#include "sim/stats.hh" 46956SN/A#include "sim/system.hh" 478229Snate@binkert.org#include "sim/debug.hh" 484078Sbinkertn@umich.edu 49299SN/Ausing namespace std; 50299SN/A 518777Sgblack@eecs.umich.eduextern SamplingCPU *SampCPU; 522170SN/A 535882Snate@binkert.orgusing namespace Stats; 546658Snate@binkert.org 556658Snate@binkert.orgnamespace AlphaPseudo 561717SN/A{ 578229Snate@binkert.org bool doStatisticsInsts; 582680Sktlim@umich.edu bool doCheckpointInsts; 598232Snate@binkert.org bool doQuiesce; 608232Snate@binkert.org 618232Snate@binkert.org void 625529Snate@binkert.org arm(ExecContext *xc) 633565Sgblack@eecs.umich.edu { 64298SN/A xc->kernelStats->arm(); 655606Snate@binkert.org } 66298SN/A 67695SN/A void 68695SN/A quiesce(ExecContext *xc) 69954SN/A { 702080SN/A if (!doQuiesce) 71298SN/A return; 72299SN/A 731052SN/A xc->suspend(); 74729SN/A xc->kernelStats->quiesce(); 752107SN/A } 76298SN/A 775504Snate@binkert.org void 785504Snate@binkert.org ivlb(ExecContext *xc) 795780Ssteve.reinhardt@amd.com { 805780Ssteve.reinhardt@amd.com xc->kernelStats->ivlb(); 815504Snate@binkert.org } 825504Snate@binkert.org 83298SN/A void 845504Snate@binkert.org ivle(ExecContext *xc) 855504Snate@binkert.org { 865504Snate@binkert.org } 875504Snate@binkert.org 885504Snate@binkert.org void 895504Snate@binkert.org m5exit_old(ExecContext *xc) 905504Snate@binkert.org { 915529Snate@binkert.org SimExit(curTick, "m5_exit_old instruction encountered"); 925504Snate@binkert.org } 935504Snate@binkert.org 945504Snate@binkert.org void 955504Snate@binkert.org m5exit(ExecContext *xc) 965504Snate@binkert.org { 975504Snate@binkert.org Tick delay = xc->regs.intRegFile[16]; 985504Snate@binkert.org Tick when = curTick + NS2Ticks(delay); 995504Snate@binkert.org SimExit(when, "m5_exit instruction encountered"); 1005504Snate@binkert.org } 1015504Snate@binkert.org 1028142SAli.Saidi@ARM.com void 1038142SAli.Saidi@ARM.com resetstats(ExecContext *xc) 1048142SAli.Saidi@ARM.com { 1058142SAli.Saidi@ARM.com if (!doStatisticsInsts) 1068142SAli.Saidi@ARM.com return; 1078142SAli.Saidi@ARM.com 1088142SAli.Saidi@ARM.com Tick delay = xc->regs.intRegFile[16]; 1098142SAli.Saidi@ARM.com Tick period = xc->regs.intRegFile[17]; 1108142SAli.Saidi@ARM.com 1118142SAli.Saidi@ARM.com Tick when = curTick + NS2Ticks(delay); 1128142SAli.Saidi@ARM.com Tick repeat = NS2Ticks(period); 1138142SAli.Saidi@ARM.com 1148142SAli.Saidi@ARM.com using namespace Stats; 1158142SAli.Saidi@ARM.com SetupEvent(Reset, when, repeat); 1168142SAli.Saidi@ARM.com } 1178142SAli.Saidi@ARM.com 1188142SAli.Saidi@ARM.com void 1198142SAli.Saidi@ARM.com dumpstats(ExecContext *xc) 1208142SAli.Saidi@ARM.com { 1218142SAli.Saidi@ARM.com if (!doStatisticsInsts) 1228142SAli.Saidi@ARM.com return; 1238142SAli.Saidi@ARM.com 1245504Snate@binkert.org Tick delay = xc->regs.intRegFile[16]; 1255504Snate@binkert.org Tick period = xc->regs.intRegFile[17]; 1267819Ssteve.reinhardt@amd.com 1277819Ssteve.reinhardt@amd.com Tick when = curTick + NS2Ticks(delay); 1287819Ssteve.reinhardt@amd.com Tick repeat = NS2Ticks(period); 1295504Snate@binkert.org 1305504Snate@binkert.org using namespace Stats; 1315504Snate@binkert.org SetupEvent(Dump, when, repeat); 1325504Snate@binkert.org } 1337823Ssteve.reinhardt@amd.com 1345504Snate@binkert.org void 1357819Ssteve.reinhardt@amd.com dumpresetstats(ExecContext *xc) 1365504Snate@binkert.org { 1375504Snate@binkert.org if (!doStatisticsInsts) 1387819Ssteve.reinhardt@amd.com return; 1395504Snate@binkert.org 1405504Snate@binkert.org Tick delay = xc->regs.intRegFile[16]; 1415504Snate@binkert.org Tick period = xc->regs.intRegFile[17]; 1425504Snate@binkert.org 1435504Snate@binkert.org Tick when = curTick + NS2Ticks(delay); 1445504Snate@binkert.org Tick repeat = NS2Ticks(period); 1455504Snate@binkert.org 1465504Snate@binkert.org using namespace Stats; 1475504Snate@binkert.org SetupEvent(Dump|Reset, when, repeat); 1487819Ssteve.reinhardt@amd.com } 1497819Ssteve.reinhardt@amd.com 1507819Ssteve.reinhardt@amd.com void 1515504Snate@binkert.org m5checkpoint(ExecContext *xc) 1525504Snate@binkert.org { 1535504Snate@binkert.org if (!doCheckpointInsts) 1545504Snate@binkert.org return; 1557823Ssteve.reinhardt@amd.com 1565504Snate@binkert.org Tick delay = xc->regs.intRegFile[16]; 1577819Ssteve.reinhardt@amd.com Tick period = xc->regs.intRegFile[17]; 1585504Snate@binkert.org 1595504Snate@binkert.org Tick when = curTick + NS2Ticks(delay); 1607819Ssteve.reinhardt@amd.com Tick repeat = NS2Ticks(period); 1615504Snate@binkert.org 1625504Snate@binkert.org Checkpoint::setup(when, repeat); 1635504Snate@binkert.org } 1645504Snate@binkert.org 1655504Snate@binkert.org void 1665504Snate@binkert.org readfile(ExecContext *xc) 1675504Snate@binkert.org { 1685504Snate@binkert.org const string &file = xc->cpu->system->params->readfile; 1695504Snate@binkert.org if (file.empty()) { 1707064Snate@binkert.org xc->regs.intRegFile[0] = ULL(0); 1717064Snate@binkert.org return; 1725504Snate@binkert.org } 1735504Snate@binkert.org 1745780Ssteve.reinhardt@amd.com Addr vaddr = xc->regs.intRegFile[16]; 1755780Ssteve.reinhardt@amd.com uint64_t len = xc->regs.intRegFile[17]; 1765741Snate@binkert.org uint64_t offset = xc->regs.intRegFile[18]; 1775741Snate@binkert.org uint64_t result = 0; 1785741Snate@binkert.org 1797823Ssteve.reinhardt@amd.com int fd = ::open(file.c_str(), O_RDONLY, 0); 1805741Snate@binkert.org if (fd < 0) 1815741Snate@binkert.org panic("could not open file %s\n", file); 1825504Snate@binkert.org 1835808Snate@binkert.org char *buf = new char[len]; 1845808Snate@binkert.org char *p = buf; 1855808Snate@binkert.org while (len > 0) { 1865808Snate@binkert.org int bytes = ::pread(fd, p, len, offset); 1875808Snate@binkert.org if (bytes <= 0) 1885808Snate@binkert.org break; 1895808Snate@binkert.org 1905808Snate@binkert.org p += bytes; 1915808Snate@binkert.org offset += bytes; 1925504Snate@binkert.org result += bytes; 1935504Snate@binkert.org len -= bytes; 1947823Ssteve.reinhardt@amd.com } 1957819Ssteve.reinhardt@amd.com 1965504Snate@binkert.org close(fd); 1975504Snate@binkert.org CopyIn(xc, vaddr, buf, result); 1985780Ssteve.reinhardt@amd.com delete [] buf; 1995780Ssteve.reinhardt@amd.com xc->regs.intRegFile[0] = result; 2005504Snate@binkert.org } 2015504Snate@binkert.org 2025504Snate@binkert.org class Context : public ParamContext 2035504Snate@binkert.org { 2045504Snate@binkert.org public: 2055504Snate@binkert.org Context(const string §ion) : ParamContext(section) {} 206711SN/A void checkParams(); 207711SN/A }; 2085504Snate@binkert.org 2095504Snate@binkert.org Context context("pseudo_inst"); 210310SN/A 2115504Snate@binkert.org Param<bool> __quiesce(&context, "quiesce", 2125504Snate@binkert.org "enable quiesce instructions", 2133373Sstever@eecs.umich.edu true); 2145504Snate@binkert.org Param<bool> __statistics(&context, "statistics", 2155504Snate@binkert.org "enable statistics pseudo instructions", 2165504Snate@binkert.org true); 2175504Snate@binkert.org Param<bool> __checkpoint(&context, "checkpoint", 2185504Snate@binkert.org "enable checkpoint pseudo instructions", 2195504Snate@binkert.org true); 2206227Snate@binkert.org 2215504Snate@binkert.org void 2225504Snate@binkert.org Context::checkParams() 2235504Snate@binkert.org { 2245504Snate@binkert.org doQuiesce = __quiesce; 2255504Snate@binkert.org doStatisticsInsts = __statistics; 2265504Snate@binkert.org doCheckpointInsts = __checkpoint; 2275504Snate@binkert.org } 2285504Snate@binkert.org 2295504Snate@binkert.org void debugbreak(ExecContext *xc) 2305504Snate@binkert.org { 2315504Snate@binkert.org debug_break(); 2325504Snate@binkert.org } 2335504Snate@binkert.org 2345504Snate@binkert.org void switchcpu(ExecContext *xc) 2355504Snate@binkert.org { 2365504Snate@binkert.org if (SampCPU) 2375504Snate@binkert.org SampCPU->switchCPUs(); 2385504Snate@binkert.org } 2395504Snate@binkert.org} 2405504Snate@binkert.org