process.hh revision 2401
12810Srdreslin@umich.edu/* 22810Srdreslin@umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 32810Srdreslin@umich.edu * All rights reserved. 42810Srdreslin@umich.edu * 52810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 62810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 72810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 82810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 92810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 102810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 112810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 122810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 132810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 142810Srdreslin@umich.edu * this software without specific prior written permission. 152810Srdreslin@umich.edu * 162810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810Srdreslin@umich.edu */ 282810Srdreslin@umich.edu 292810Srdreslin@umich.edu#ifndef __PROCESS_HH__ 302810Srdreslin@umich.edu#define __PROCESS_HH__ 312810Srdreslin@umich.edu 322810Srdreslin@umich.edu// 332810Srdreslin@umich.edu// The purpose of this code is to fake the loader & syscall mechanism 342810Srdreslin@umich.edu// when there's no OS: thus there's no reason to use it in FULL_SYSTEM 352810Srdreslin@umich.edu// mode when we do have an OS. 362810Srdreslin@umich.edu// 372810Srdreslin@umich.edu#include "config/full_system.hh" 382810Srdreslin@umich.edu 392810Srdreslin@umich.edu#if !FULL_SYSTEM 402810Srdreslin@umich.edu 412810Srdreslin@umich.edu#include <vector> 422814Srdreslin@umich.edu 432810Srdreslin@umich.edu#include "base/statistics.hh" 442810Srdreslin@umich.edu#include "base/trace.hh" 452810Srdreslin@umich.edu#include "mem/memory.hh" 462810Srdreslin@umich.edu//#include "mem/mem_interface.hh" 472810Srdreslin@umich.edu#include "mem/page_table.hh" 482810Srdreslin@umich.edu#include "sim/sim_object.hh" 492810Srdreslin@umich.edu#include "sim/stats.hh" 502810Srdreslin@umich.edu#include "targetarch/isa_traits.hh" 512810Srdreslin@umich.edu 522810Srdreslin@umich.educlass ExecContext; 532810Srdreslin@umich.educlass TranslatingPort; 542810Srdreslin@umich.educlass System; 552810Srdreslin@umich.edu 562810Srdreslin@umich.educlass Process : public SimObject 572810Srdreslin@umich.edu{ 582810Srdreslin@umich.edu public: 592810Srdreslin@umich.edu 602810Srdreslin@umich.edu /// Pointer to object representing the system this process is 612810Srdreslin@umich.edu /// running on. 622810Srdreslin@umich.edu System *system; 632810Srdreslin@umich.edu 642810Srdreslin@umich.edu // have we initialized an execution context from this process? If 652810Srdreslin@umich.edu // yes, subsequent contexts are assumed to be for dynamically 662810Srdreslin@umich.edu // created threads and are not initialized. 672810Srdreslin@umich.edu bool initialContextLoaded; 682810Srdreslin@umich.edu 692810Srdreslin@umich.edu // execution contexts associated with this process 702810Srdreslin@umich.edu std::vector<ExecContext *> execContexts; 712810Srdreslin@umich.edu 722810Srdreslin@umich.edu // number of CPUs (esxec contexts, really) assigned to this process. 732810Srdreslin@umich.edu unsigned int numCpus() { return execContexts.size(); } 742810Srdreslin@umich.edu 752810Srdreslin@umich.edu // record of blocked context 762810Srdreslin@umich.edu struct WaitRec 772810Srdreslin@umich.edu { 782810Srdreslin@umich.edu Addr waitChan; 792810Srdreslin@umich.edu ExecContext *waitingContext; 802810Srdreslin@umich.edu 812810Srdreslin@umich.edu WaitRec(Addr chan, ExecContext *ctx) 822810Srdreslin@umich.edu : waitChan(chan), waitingContext(ctx) 832810Srdreslin@umich.edu { } 842810Srdreslin@umich.edu }; 852810Srdreslin@umich.edu 862810Srdreslin@umich.edu // list of all blocked contexts 872810Srdreslin@umich.edu std::list<WaitRec> waitList; 882810Srdreslin@umich.edu 892810Srdreslin@umich.edu Addr text_base; // text (code) segment base 902810Srdreslin@umich.edu unsigned text_size; // text (code) size in bytes 912810Srdreslin@umich.edu 922810Srdreslin@umich.edu Addr data_base; // initialized data segment base 932810Srdreslin@umich.edu unsigned data_size; // initialized data + bss size in bytes 942810Srdreslin@umich.edu 952810Srdreslin@umich.edu Addr brk_point; // top of the data segment 962810Srdreslin@umich.edu 972810Srdreslin@umich.edu Addr stack_base; // stack segment base (highest address) 982810Srdreslin@umich.edu unsigned stack_size; // initial stack size 992810Srdreslin@umich.edu Addr stack_min; // lowest address accessed on the stack 1002810Srdreslin@umich.edu 1012810Srdreslin@umich.edu // addr to use for next stack region (for multithreaded apps) 1022810Srdreslin@umich.edu Addr next_thread_stack_base; 1032810Srdreslin@umich.edu 1042810Srdreslin@umich.edu // Base of region for mmaps (when user doesn't specify an address). 1052810Srdreslin@umich.edu Addr mmap_start; 1062810Srdreslin@umich.edu Addr mmap_end; 1072810Srdreslin@umich.edu 1082810Srdreslin@umich.edu // Base of region for nxm data 1092810Srdreslin@umich.edu Addr nxm_start; 1102810Srdreslin@umich.edu Addr nxm_end; 1112810Srdreslin@umich.edu 1122810Srdreslin@umich.edu std::string prog_fname; // file name 1132810Srdreslin@umich.edu Addr prog_entry; // entry point (initial PC) 1142810Srdreslin@umich.edu 1152810Srdreslin@umich.edu Stats::Scalar<> num_syscalls; // number of syscalls executed 1162810Srdreslin@umich.edu 1172810Srdreslin@umich.edu 1182810Srdreslin@umich.edu protected: 1192810Srdreslin@umich.edu // constructor 1202810Srdreslin@umich.edu Process(const std::string &nm, 1212810Srdreslin@umich.edu System *_system, 1222810Srdreslin@umich.edu int stdin_fd, // initial I/O descriptors 1232810Srdreslin@umich.edu int stdout_fd, 1242810Srdreslin@umich.edu int stderr_fd); 1252810Srdreslin@umich.edu 1262810Srdreslin@umich.edu // post initialization startup 1272810Srdreslin@umich.edu virtual void startup(); 1282810Srdreslin@umich.edu 1292810Srdreslin@umich.edu protected: 1302810Srdreslin@umich.edu /// Memory object for initialization (image loading) 1312810Srdreslin@umich.edu TranslatingPort *initVirtMem; 1322810Srdreslin@umich.edu 1332810Srdreslin@umich.edu public: 1342810Srdreslin@umich.edu PageTable *pTable; 1352810Srdreslin@umich.edu 1362810Srdreslin@umich.edu private: 1372810Srdreslin@umich.edu // file descriptor remapping support 1382810Srdreslin@umich.edu static const int MAX_FD = 256; // max legal fd value 1392810Srdreslin@umich.edu int fd_map[MAX_FD+1]; 1402810Srdreslin@umich.edu 1412810Srdreslin@umich.edu public: 1422810Srdreslin@umich.edu // static helper functions to generate file descriptors for constructor 1432810Srdreslin@umich.edu static int openInputFile(const std::string &filename); 1442810Srdreslin@umich.edu static int openOutputFile(const std::string &filename); 1452810Srdreslin@umich.edu 1462810Srdreslin@umich.edu // override of virtual SimObject method: register statistics 1472810Srdreslin@umich.edu virtual void regStats(); 1482991Srdreslin@umich.edu 1492810Srdreslin@umich.edu // register an execution context for this process. 1502810Srdreslin@umich.edu // returns xc's cpu number (index into execContexts[]) 1512810Srdreslin@umich.edu int registerExecContext(ExecContext *xc); 1522810Srdreslin@umich.edu 1532810Srdreslin@umich.edu 1542810Srdreslin@umich.edu void replaceExecContext(ExecContext *xc, int xcIndex); 1552810Srdreslin@umich.edu 1563862Sstever@eecs.umich.edu // map simulator fd sim_fd to target fd tgt_fd 1572810Srdreslin@umich.edu void dup_fd(int sim_fd, int tgt_fd); 1582810Srdreslin@umich.edu 1592810Srdreslin@umich.edu // generate new target fd for sim_fd 1602810Srdreslin@umich.edu int alloc_fd(int sim_fd); 1612810Srdreslin@umich.edu 1622810Srdreslin@umich.edu // free target fd (e.g., after close) 1632810Srdreslin@umich.edu void free_fd(int tgt_fd); 1642810Srdreslin@umich.edu 1652810Srdreslin@umich.edu // look up simulator fd for given target fd 1662991Srdreslin@umich.edu int sim_fd(int tgt_fd); 1672810Srdreslin@umich.edu 1682810Srdreslin@umich.edu // is this a valid instruction fetch address? 1692810Srdreslin@umich.edu bool validInstAddr(Addr addr) 1702810Srdreslin@umich.edu { 1712810Srdreslin@umich.edu return (text_base <= addr && 1722810Srdreslin@umich.edu addr < text_base + text_size && 1732810Srdreslin@umich.edu !(addr & (sizeof(MachInst)-1))); 1742810Srdreslin@umich.edu } 1752810Srdreslin@umich.edu 1762810Srdreslin@umich.edu // is this a valid address? (used to filter data fetches) 1772810Srdreslin@umich.edu // note that we just assume stack size <= 16MB 1782810Srdreslin@umich.edu // this may be alpha-specific 1792810Srdreslin@umich.edu bool validDataAddr(Addr addr) 1802810Srdreslin@umich.edu { 1812810Srdreslin@umich.edu return ((data_base <= addr && addr < brk_point) || 1822810Srdreslin@umich.edu (next_thread_stack_base <= addr && addr < stack_base) || 1832810Srdreslin@umich.edu (text_base <= addr && addr < (text_base + text_size)) || 1842810Srdreslin@umich.edu (mmap_start <= addr && addr < mmap_end) || 1852810Srdreslin@umich.edu (nxm_start <= addr && addr < nxm_end)); 1862810Srdreslin@umich.edu } 1872810Srdreslin@umich.edu 1882810Srdreslin@umich.edu virtual void syscall(ExecContext *xc) = 0; 1892810Srdreslin@umich.edu}; 1902810Srdreslin@umich.edu 1912810Srdreslin@umich.edu// 1922810Srdreslin@umich.edu// "Live" process with system calls redirected to host system 1932810Srdreslin@umich.edu// 1942810Srdreslin@umich.educlass ObjectFile; 1952810Srdreslin@umich.educlass LiveProcess : public Process 1962810Srdreslin@umich.edu{ 1972810Srdreslin@umich.edu protected: 1982810Srdreslin@umich.edu ObjectFile *objFile; 1992810Srdreslin@umich.edu std::vector<std::string> argv; 2002810Srdreslin@umich.edu std::vector<std::string> envp; 2012810Srdreslin@umich.edu 2022810Srdreslin@umich.edu LiveProcess(const std::string &nm, ObjectFile *objFile, 2032810Srdreslin@umich.edu System *_system, int stdin_fd, int stdout_fd, int stderr_fd, 2042991Srdreslin@umich.edu std::vector<std::string> &argv, 2052810Srdreslin@umich.edu std::vector<std::string> &envp); 2062810Srdreslin@umich.edu 2072810Srdreslin@umich.edu void startup(); 2082810Srdreslin@umich.edu 2092810Srdreslin@umich.edu public: 2102810Srdreslin@umich.edu // this function is used to create the LiveProcess object, since 2112810Srdreslin@umich.edu // we can't tell which subclass of LiveProcess to use until we 2122810Srdreslin@umich.edu // open and look at the object file. 2132810Srdreslin@umich.edu static LiveProcess *create(const std::string &nm, 2142810Srdreslin@umich.edu System *_system, 2152810Srdreslin@umich.edu int stdin_fd, int stdout_fd, int stderr_fd, 2162810Srdreslin@umich.edu std::string executable, 2172810Srdreslin@umich.edu std::vector<std::string> &argv, 2184626Sstever@eecs.umich.edu std::vector<std::string> &envp); 2192810Srdreslin@umich.edu}; 2202810Srdreslin@umich.edu 2212810Srdreslin@umich.edu 2222810Srdreslin@umich.edu#endif // !FULL_SYSTEM 2232810Srdreslin@umich.edu 2244626Sstever@eecs.umich.edu#endif // __PROCESS_HH__ 2252810Srdreslin@umich.edu