mem.hh revision 12188
12789Sktlim@umich.edu/* 212355Snikos.nikoleris@arm.com * Copyright (c) 2015 ARM Limited 38733Sgeoffrey.blake@arm.com * All rights reserved 48733Sgeoffrey.blake@arm.com * 58733Sgeoffrey.blake@arm.com * The license below extends only to copyright in the software and shall 68733Sgeoffrey.blake@arm.com * not be construed as granting a license to any other intellectual 78733Sgeoffrey.blake@arm.com * property including but not limited to intellectual property relating 88733Sgeoffrey.blake@arm.com * to a hardware implementation of the functionality of the software 98733Sgeoffrey.blake@arm.com * licensed hereunder. You may use the software subject to the license 108733Sgeoffrey.blake@arm.com * terms below provided that you ensure that this notice is replicated 118733Sgeoffrey.blake@arm.com * unmodified and in its entirety in all distributions of the software, 128733Sgeoffrey.blake@arm.com * modified or unmodified, in source code or in binary form. 138733Sgeoffrey.blake@arm.com * 142789Sktlim@umich.edu * Redistribution and use in source and binary forms, with or without 152789Sktlim@umich.edu * modification, are permitted provided that the following conditions are 162789Sktlim@umich.edu * met: redistributions of source code must retain the above copyright 172789Sktlim@umich.edu * notice, this list of conditions and the following disclaimer; 182789Sktlim@umich.edu * redistributions in binary form must reproduce the above copyright 192789Sktlim@umich.edu * notice, this list of conditions and the following disclaimer in the 202789Sktlim@umich.edu * documentation and/or other materials provided with the distribution; 212789Sktlim@umich.edu * neither the name of the copyright holders nor the names of its 222789Sktlim@umich.edu * contributors may be used to endorse or promote products derived from 232789Sktlim@umich.edu * this software without specific prior written permission. 242789Sktlim@umich.edu * 252789Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 262789Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 272789Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 282789Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 292789Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 302789Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 312789Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 322789Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 332789Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 342789Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 352789Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 362789Sktlim@umich.edu * 372789Sktlim@umich.edu * Authors: Andreas Sandberg 382789Sktlim@umich.edu */ 392789Sktlim@umich.edu#ifndef __SIM_PROBE_MEM_HH__ 402789Sktlim@umich.edu#define __SIM_PROBE_MEM_HH__ 418733Sgeoffrey.blake@arm.com 422789Sktlim@umich.edu#include <memory> 432789Sktlim@umich.edu 4411793Sbrandon.potter@amd.com#include "mem/packet.hh" 4511793Sbrandon.potter@amd.com#include "sim/probe/probe.hh" 462789Sktlim@umich.edu 472789Sktlim@umich.edunamespace ProbePoints { 482789Sktlim@umich.edu 4910687SAndreas.Sandberg@ARM.com/** 508793Sgblack@eecs.umich.edu * A struct to hold on to the essential fields from a packet, so that 518793Sgblack@eecs.umich.edu * the packet and underlying request can be safely passed on, and 522789Sktlim@umich.edu * consequently modified or even deleted. 532789Sktlim@umich.edu */ 543348Sbinkertn@umich.edustruct PacketInfo { 552789Sktlim@umich.edu MemCmd cmd; 568733Sgeoffrey.blake@arm.com Addr addr; 578887Sgeoffrey.blake@arm.com uint32_t size; 582789Sktlim@umich.edu Request::FlagsType flags; 592789Sktlim@umich.edu Addr pc; 608733Sgeoffrey.blake@arm.com MasterID master; 612789Sktlim@umich.edu 622789Sktlim@umich.edu explicit PacketInfo(const PacketPtr& pkt) : 632789Sktlim@umich.edu cmd(pkt->cmd), 642789Sktlim@umich.edu addr(pkt->getAddr()), 6512680Sgiacomo.travaglini@arm.com size(pkt->getSize()), 662789Sktlim@umich.edu flags(pkt->req->getFlags()), 672789Sktlim@umich.edu pc(pkt->req->hasPC() ? pkt->req->getPC() : 0), 682789Sktlim@umich.edu master(pkt->req->masterId()) { } 699176Sandreas.hansson@arm.com}; 709176Sandreas.hansson@arm.com 712789Sktlim@umich.edu/** 722789Sktlim@umich.edu * Packet probe point 738733Sgeoffrey.blake@arm.com * 748733Sgeoffrey.blake@arm.com * This probe point provides a unified interface for components that 752789Sktlim@umich.edu * want to instrument Packets in the memory system. Components should 762789Sktlim@umich.edu * when possible adhere to the following naming scheme: 772789Sktlim@umich.edu * 782789Sktlim@umich.edu * <ul> 792789Sktlim@umich.edu * 802789Sktlim@umich.edu * <li>PktRequest: Requests sent out on the memory side of a normal 812789Sktlim@umich.edu * components and incoming requests for memories. Packets should 8210034SGeoffrey.Blake@arm.com * not be duplicated (i.e., a packet should only appear once 832789Sktlim@umich.edu * irrespective of the receiving end requesting a retry). 842789Sktlim@umich.edu * 852789Sktlim@umich.edu * <li>PktResponse: Response received from the memory side of a 862789Sktlim@umich.edu * normal component or a response being sent out from a memory. 872789Sktlim@umich.edu * 888733Sgeoffrey.blake@arm.com * <li>PktRequestCPU: Incoming, accepted, memory request on the CPU 892789Sktlim@umich.edu * side of a two-sided component. This probe point is primarily 908733Sgeoffrey.blake@arm.com * intended for components that cache or forward requests (e.g., 912789Sktlim@umich.edu * caches and XBars), single-sided components should use 922789Sktlim@umich.edu * PktRequest instead. The probe point should only be called 932789Sktlim@umich.edu * when a packet is accepted. 942789Sktlim@umich.edu * 952789Sktlim@umich.edu * <li>PktResponseCPU: Outgoing response memory request on the CPU 962789Sktlim@umich.edu * side of a two-sided component. This probe point is primarily 972789Sktlim@umich.edu * intended for components that cache or forward requests (e.g., 982789Sktlim@umich.edu * caches and XBars), single-sided components should use 992789Sktlim@umich.edu * PktRequest instead. 1009384SAndreas.Sandberg@arm.com * 1019384SAndreas.Sandberg@arm.com * </ul> 1022789Sktlim@umich.edu * 1032789Sktlim@umich.edu */ 1048887Sgeoffrey.blake@arm.comtypedef ProbePointArg<PacketInfo> Packet; 1059384SAndreas.Sandberg@arm.comtypedef std::unique_ptr<Packet> PacketUPtr; 1069384SAndreas.Sandberg@arm.com 1078887Sgeoffrey.blake@arm.com} 1088887Sgeoffrey.blake@arm.com 1098887Sgeoffrey.blake@arm.com#endif 1109384SAndreas.Sandberg@arm.com