faults.cc revision 2800
12SN/A/*
21762SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan
32SN/A * All rights reserved.
42SN/A *
52SN/A * Redistribution and use in source and binary forms, with or without
62SN/A * modification, are permitted provided that the following conditions are
72SN/A * met: redistributions of source code must retain the above copyright
82SN/A * notice, this list of conditions and the following disclaimer;
92SN/A * redistributions in binary form must reproduce the above copyright
102SN/A * notice, this list of conditions and the following disclaimer in the
112SN/A * documentation and/or other materials provided with the distribution;
122SN/A * neither the name of the copyright holders nor the names of its
132SN/A * contributors may be used to endorse or promote products derived from
142SN/A * this software without specific prior written permission.
152SN/A *
162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert
292665Ssaidi@eecs.umich.edu *          Gabe Black
302SN/A */
312SN/A
322439SN/A#include "base/misc.hh"
332090SN/A#include "sim/faults.hh"
342680Sktlim@umich.edu#include "cpu/thread_context.hh"
352222SN/A#include "cpu/base.hh"
362SN/A
372201SN/A#if !FULL_SYSTEM
382680Sktlim@umich.eduvoid FaultBase::invoke(ThreadContext * tc)
392201SN/A{
402680Sktlim@umich.edu    fatal("fault (%s) detected @ PC 0x%08p", name(), tc->readPC());
412201SN/A}
422222SN/A#else
432680Sktlim@umich.eduvoid FaultBase::invoke(ThreadContext * tc)
442222SN/A{
452680Sktlim@umich.edu    DPRINTF(Fault, "Fault %s at PC: %#x\n", name(), tc->readPC());
462680Sktlim@umich.edu    tc->getCpuPtr()->recordEvent(csprintf("Fault %s", name()));
472222SN/A
482680Sktlim@umich.edu    assert(!tc->misspeculating());
492222SN/A}
502201SN/A#endif
512612SN/A
522680Sktlim@umich.eduvoid UnimpFault::invoke(ThreadContext * tc)
532612SN/A{
542612SN/A    panic("Unimpfault: %s\n", panicStr.c_str());
552612SN/A}
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