debug.cc revision 11157
12SN/A/* 21762SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 292665Ssaidi@eecs.umich.edu * Steve Reinhardt 302SN/A */ 312SN/A 322SN/A#include <string> 332SN/A#include <vector> 342SN/A 355882Snate@binkert.org#include "base/debug.hh" 3656SN/A#include "sim/debug.hh" 379356Snilay@cs.wisc.edu#include "sim/eventq_impl.hh" 389983Sstever@gmail.com#include "sim/global_event.hh" 3956SN/A#include "sim/sim_events.hh" 408278SAli.Saidi@ARM.com#include "sim/sim_exit.hh" 4111157SDylan.Johnson@ARM.com#include "cpu/pc_event.hh" 4211157SDylan.Johnson@ARM.com#include "sim/system.hh" 432SN/A 442SN/Ausing namespace std; 452SN/A 462SN/A// 472SN/A// Debug event: place a breakpoint on the process function and 482SN/A// schedule the event to break at a particular cycle 492SN/A// 509983Sstever@gmail.comstruct DebugBreakEvent : public GlobalEvent 512SN/A{ 529983Sstever@gmail.com DebugBreakEvent(Tick when); 535543Ssaidi@eecs.umich.edu void process(); // process event 545336Shines@cs.fsu.edu virtual const char *description() const; 552SN/A}; 562SN/A 572SN/A// 582SN/A// constructor: schedule at specified time 592SN/A// 609983Sstever@gmail.comDebugBreakEvent::DebugBreakEvent(Tick when) 619983Sstever@gmail.com : GlobalEvent(when, Debug_Break_Pri, AutoDelete) 622SN/A{ 632SN/A} 642SN/A 652SN/A// 662SN/A// handle debug event: set debugger breakpoint on this function 672SN/A// 682SN/Avoid 692SN/ADebugBreakEvent::process() 702SN/A{ 718231Snate@binkert.org Debug::breakpoint(); 722SN/A} 732SN/A 742SN/A 752SN/Aconst char * 765336Shines@cs.fsu.eduDebugBreakEvent::description() const 772SN/A{ 788231Snate@binkert.org return "debug breakpoint"; 792SN/A} 802SN/A 812SN/A// 822SN/A// handy function to schedule DebugBreakEvent on main event queue 832SN/A// (callable from debugger) 842SN/A// 853645Sbinkertn@umich.eduvoid 869960Sandreas.hansson@arm.comschedBreak(Tick when) 872SN/A{ 889983Sstever@gmail.com new DebugBreakEvent(when); 895606Snate@binkert.org warn("need to stop all queues"); 902SN/A} 912SN/A 9211157SDylan.Johnson@ARM.comvoid 9311157SDylan.Johnson@ARM.combreakAtKernelFunction(const char* funcName) 9411157SDylan.Johnson@ARM.com{ 9511157SDylan.Johnson@ARM.com System* curSystem = System::systemList[0]; 9611157SDylan.Johnson@ARM.com curSystem->addKernelFuncEvent<BreakPCEvent>(funcName, 9711157SDylan.Johnson@ARM.com "GDB scheduled break", true); 9811157SDylan.Johnson@ARM.com} 9911157SDylan.Johnson@ARM.com 1008278SAli.Saidi@ARM.com/// 1018278SAli.Saidi@ARM.com/// Function to cause the simulator to take a checkpoint from the debugger 1028278SAli.Saidi@ARM.com/// 1038278SAli.Saidi@ARM.comvoid 1048278SAli.Saidi@ARM.comtakeCheckpoint(Tick when) 1058278SAli.Saidi@ARM.com{ 1068278SAli.Saidi@ARM.com if (!when) 1078278SAli.Saidi@ARM.com when = curTick() + 1; 1088278SAli.Saidi@ARM.com exitSimLoop("checkpoint", 0, when, 0); 1098278SAli.Saidi@ARM.com} 1108278SAli.Saidi@ARM.com 1113645Sbinkertn@umich.eduvoid 1123645Sbinkertn@umich.edueventqDump() 1132SN/A{ 1149983Sstever@gmail.com for (uint32_t i = 0; i < numMainEventQueues; ++i) { 1159983Sstever@gmail.com mainEventQueue[i]->dump(); 1169983Sstever@gmail.com } 1172SN/A} 1182SN/A 1195512SMichael.Adler@intel.comint remote_gdb_base_port = 7000; 1205512SMichael.Adler@intel.com 1215512SMichael.Adler@intel.comint 1225512SMichael.Adler@intel.comgetRemoteGDBPort() 1235512SMichael.Adler@intel.com{ 1245512SMichael.Adler@intel.com return remote_gdb_base_port; 1255512SMichael.Adler@intel.com} 1265512SMichael.Adler@intel.com 1275512SMichael.Adler@intel.com// Set remote GDB base port. 0 means disable remote GDB. 1285512SMichael.Adler@intel.com// Callable from python. 1295512SMichael.Adler@intel.comvoid 1305512SMichael.Adler@intel.comsetRemoteGDBPort(int port) 1315512SMichael.Adler@intel.com{ 1325512SMichael.Adler@intel.com remote_gdb_base_port = port; 1335512SMichael.Adler@intel.com} 1345512SMichael.Adler@intel.com 135