System.py revision 10282:3ea92bc6393b
19651SAndreas.Sandberg@ARM.com# Copyright (c) 2005-2007 The Regents of The University of Michigan 210858Sandreas.sandberg@arm.com# Copyright (c) 2011 Regents of the University of California 39651SAndreas.Sandberg@ARM.com# All rights reserved. 49651SAndreas.Sandberg@ARM.com# 59651SAndreas.Sandberg@ARM.com# Redistribution and use in source and binary forms, with or without 69651SAndreas.Sandberg@ARM.com# modification, are permitted provided that the following conditions are 79651SAndreas.Sandberg@ARM.com# met: redistributions of source code must retain the above copyright 89651SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer; 99651SAndreas.Sandberg@ARM.com# redistributions in binary form must reproduce the above copyright 109651SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer in the 119651SAndreas.Sandberg@ARM.com# documentation and/or other materials provided with the distribution; 129651SAndreas.Sandberg@ARM.com# neither the name of the copyright holders nor the names of its 139651SAndreas.Sandberg@ARM.com# contributors may be used to endorse or promote products derived from 149651SAndreas.Sandberg@ARM.com# this software without specific prior written permission. 159651SAndreas.Sandberg@ARM.com# 169651SAndreas.Sandberg@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 179651SAndreas.Sandberg@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 189651SAndreas.Sandberg@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 199651SAndreas.Sandberg@ARM.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 209651SAndreas.Sandberg@ARM.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 219651SAndreas.Sandberg@ARM.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 229651SAndreas.Sandberg@ARM.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 239651SAndreas.Sandberg@ARM.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 249651SAndreas.Sandberg@ARM.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 259651SAndreas.Sandberg@ARM.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 269651SAndreas.Sandberg@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 279651SAndreas.Sandberg@ARM.com# 289651SAndreas.Sandberg@ARM.com# Authors: Nathan Binkert 299651SAndreas.Sandberg@ARM.com# Rick Strong 309651SAndreas.Sandberg@ARM.com 319651SAndreas.Sandberg@ARM.comfrom m5.SimObject import SimObject 329651SAndreas.Sandberg@ARM.comfrom m5.defines import buildEnv 339651SAndreas.Sandberg@ARM.comfrom m5.params import * 349651SAndreas.Sandberg@ARM.comfrom m5.proxy import * 359651SAndreas.Sandberg@ARM.com 369651SAndreas.Sandberg@ARM.comfrom DVFSHandler import * 379651SAndreas.Sandberg@ARM.comfrom SimpleMemory import * 389651SAndreas.Sandberg@ARM.com 399651SAndreas.Sandberg@ARM.comclass MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing', 4011793Sbrandon.potter@amd.com 'atomic_noncaching'] 4111793Sbrandon.potter@amd.com 429651SAndreas.Sandberg@ARM.comclass System(MemObject): 439651SAndreas.Sandberg@ARM.com type = 'System' 449651SAndreas.Sandberg@ARM.com cxx_header = "sim/system.hh" 459651SAndreas.Sandberg@ARM.com system_port = MasterPort("System port") 469651SAndreas.Sandberg@ARM.com 479651SAndreas.Sandberg@ARM.com @classmethod 489651SAndreas.Sandberg@ARM.com def export_method_cxx_predecls(cls, code): 499651SAndreas.Sandberg@ARM.com code('#include "sim/system.hh"') 509651SAndreas.Sandberg@ARM.com 519760Sandreas@sandberg.pp.se @classmethod 529651SAndreas.Sandberg@ARM.com def export_methods(cls, code): 539683Sandreas@sandberg.pp.se code(''' 549753Sandreas@sandberg.pp.se Enums::MemoryMode getMemoryMode() const; 559651SAndreas.Sandberg@ARM.com void setMemoryMode(Enums::MemoryMode mode); 569651SAndreas.Sandberg@ARM.com''') 579651SAndreas.Sandberg@ARM.com 589651SAndreas.Sandberg@ARM.com memories = VectorParam.AbstractMemory(Self.all, 599651SAndreas.Sandberg@ARM.com "All memories in the system") 609651SAndreas.Sandberg@ARM.com mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in") 619651SAndreas.Sandberg@ARM.com 629651SAndreas.Sandberg@ARM.com # The memory ranges are to be populated when creating the system 639651SAndreas.Sandberg@ARM.com # such that these can be passed from the I/O subsystem through an 649651SAndreas.Sandberg@ARM.com # I/O bridge or cache 659651SAndreas.Sandberg@ARM.com mem_ranges = VectorParam.AddrRange([], "Ranges that constitute main memory") 669651SAndreas.Sandberg@ARM.com 6711839SCurtis.Dunham@arm.com cache_line_size = Param.Unsigned(64, "Cache line size in bytes") 689651SAndreas.Sandberg@ARM.com 699651SAndreas.Sandberg@ARM.com work_item_id = Param.Int(-1, "specific work item id") 709651SAndreas.Sandberg@ARM.com num_work_ids = Param.Int(16, "Number of distinct work item types") 7111399Sandreas.sandberg@arm.com work_begin_cpu_id_exit = Param.Int(-1, 729652SAndreas.Sandberg@ARM.com "work started on specific id, now exit simulation") 739652SAndreas.Sandberg@ARM.com work_begin_ckpt_count = Param.Counter(0, 749651SAndreas.Sandberg@ARM.com "create checkpoint when work items begin count value is reached") 759651SAndreas.Sandberg@ARM.com work_begin_exit_count = Param.Counter(0, 769651SAndreas.Sandberg@ARM.com "exit simulation when work items begin count value is reached") 7712128Sspwilson2@wisc.edu work_end_ckpt_count = Param.Counter(0, 7812128Sspwilson2@wisc.edu "create checkpoint when work items end count value is reached") 799892Sandreas@sandberg.pp.se work_end_exit_count = Param.Counter(0, 809655SAndreas.Sandberg@ARM.com "exit simulation when work items end count value is reached") 819752Sandreas@sandberg.pp.se work_cpus_ckpt_count = Param.Counter(0, 829752Sandreas@sandberg.pp.se "create checkpoint when active cpu count value is reached") 839651SAndreas.Sandberg@ARM.com 849651SAndreas.Sandberg@ARM.com init_param = Param.UInt64(0, "numerical value to pass into simulator") 859651SAndreas.Sandberg@ARM.com boot_osflags = Param.String("a", "boot flags to pass to the kernel") 869651SAndreas.Sandberg@ARM.com kernel = Param.String("", "file that contains the kernel code") 879651SAndreas.Sandberg@ARM.com kernel_addr_check = Param.Bool(True, 8810553Salexandru.dutu@amd.com "whether to address check on kernel (disable for baremetal)") 8910553Salexandru.dutu@amd.com readfile = Param.String("", "file to read startup script from") 9010553Salexandru.dutu@amd.com symbolfile = Param.String("", "file to get the symbols from") 9110553Salexandru.dutu@amd.com load_addr_mask = Param.UInt64(0xffffffffff, 9210553Salexandru.dutu@amd.com "Address to mask loading binaries with") 9310553Salexandru.dutu@amd.com load_offset = Param.UInt64(0, "Address to offset loading binaries with") 9410553Salexandru.dutu@amd.com 9510553Salexandru.dutu@amd.com # Dynamic voltage and frequency handler for the system, disabled by default 969651SAndreas.Sandberg@ARM.com # Provide list of domains that need to be controlled by the handler 979651SAndreas.Sandberg@ARM.com dvfs_handler = DVFSHandler() 989651SAndreas.Sandberg@ARM.com