System.py revision 9408 
1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# Copyright (c) 2011 Regents of the University of California
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
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9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
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13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Nathan Binkert
29#          Rick Strong
30
31from m5.SimObject import SimObject
32from m5.defines import buildEnv
33from m5.params import *
34from m5.proxy import *
35
36from SimpleMemory import *
37
38class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing']
39
40class System(MemObject):
41    type = 'System'
42    cxx_header = "sim/system.hh"
43    system_port = MasterPort("System port")
44
45    # Override the clock from the ClockedObject which looks at the
46    # parent clock by default. The 1 GHz default system clock serves
47    # as a start for the modules that rely on the parent to provide
48    # the clock.
49    clock = '1GHz'
50
51    @classmethod
52    def export_method_cxx_predecls(cls, code):
53        code('#include "sim/system.hh"')
54
55    @classmethod
56    def export_methods(cls, code):
57        code('''
58      Enums::MemoryMode getMemoryMode();
59      void setMemoryMode(Enums::MemoryMode mode);
60''')
61
62    memories = VectorParam.AbstractMemory(Self.all,
63                                          "All memories in the system")
64    mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in")
65
66    # The memory ranges are to be populated when creating the system
67    # such that these can be passed from the I/O subsystem through an
68    # I/O bridge or cache
69    mem_ranges = VectorParam.AddrRange([], "Ranges that constitute main memory")
70
71    work_item_id = Param.Int(-1, "specific work item id")
72    num_work_ids = Param.Int(16, "Number of distinct work item types")
73    work_begin_cpu_id_exit = Param.Int(-1,
74        "work started on specific id, now exit simulation")
75    work_begin_ckpt_count = Param.Counter(0,
76        "create checkpoint when work items begin count value is reached")
77    work_begin_exit_count = Param.Counter(0,
78        "exit simulation when work items begin count value is reached")
79    work_end_ckpt_count = Param.Counter(0,
80        "create checkpoint when work items end count value is reached")
81    work_end_exit_count = Param.Counter(0,
82        "exit simulation when work items end count value is reached")
83    work_cpus_ckpt_count = Param.Counter(0,
84        "create checkpoint when active cpu count value is reached")
85
86    init_param = Param.UInt64(0, "numerical value to pass into simulator")
87    boot_osflags = Param.String("a", "boot flags to pass to the kernel")
88    kernel = Param.String("", "file that contains the kernel code")
89    readfile = Param.String("", "file to read startup script from")
90    symbolfile = Param.String("", "file to get the symbols from")
91    load_addr_mask = Param.UInt64(0xffffffffff,
92            "Address to mask loading binaries with");
93