SConscript revision 9827:f47274776aa0 
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright
9# notice, this list of conditions and the following disclaimer;
10# redistributions in binary form must reproduce the above copyright
11# notice, this list of conditions and the following disclaimer in the
12# documentation and/or other materials provided with the distribution;
13# neither the name of the copyright holders nor the names of its
14# contributors may be used to endorse or promote products derived from
15# this software without specific prior written permission.
16#
17# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28#
29# Authors: Nathan Binkert
30
31Import('*')
32
33SimObject('BaseTLB.py')
34SimObject('ClockedObject.py')
35SimObject('Root.py')
36SimObject('InstTracer.py')
37SimObject('ClockDomain.py')
38SimObject('VoltageDomain.py')
39
40Source('arguments.cc')
41Source('async.cc')
42Source('core.cc')
43Source('debug.cc')
44Source('eventq.cc')
45Source('init.cc')
46Source('main.cc', main=True, skip_lib=True)
47Source('root.cc')
48Source('serialize.cc')
49Source('drain.cc')
50Source('sim_events.cc')
51Source('sim_object.cc')
52Source('simulate.cc')
53Source('stat_control.cc')
54Source('syscall_emul.cc')
55Source('clock_domain.cc')
56Source('voltage_domain.cc')
57
58if env['TARGET_ISA'] != 'no':
59    SimObject('Process.py')
60    SimObject('System.py')
61    Source('faults.cc')
62    Source('process.cc')
63    Source('pseudo_inst.cc')
64    Source('system.cc')
65
66if env['TARGET_ISA'] != 'no':
67    Source('tlb.cc')
68
69DebugFlag('Checkpoint')
70DebugFlag('Config')
71DebugFlag('Drain')
72DebugFlag('Event')
73DebugFlag('Fault')
74DebugFlag('Flow')
75DebugFlag('IPI')
76DebugFlag('IPR')
77DebugFlag('Interrupt')
78DebugFlag('Loader')
79DebugFlag('PseudoInst')
80DebugFlag('Stack')
81DebugFlag('SyscallVerbose')
82DebugFlag('TimeSync')
83DebugFlag('TLB')
84DebugFlag('Thread')
85DebugFlag('Timer')
86DebugFlag('VtoPhys')
87DebugFlag('WorkItems')
88DebugFlag('ClockDomain')
89DebugFlag('VoltageDomain')
90