xbar.hh revision 9715
12817Sksewell@umich.edu/* 22817Sksewell@umich.edu * Copyright (c) 2011-2013 ARM Limited 32817Sksewell@umich.edu * All rights reserved 42817Sksewell@umich.edu * 52817Sksewell@umich.edu * The license below extends only to copyright in the software and shall 62817Sksewell@umich.edu * not be construed as granting a license to any other intellectual 72817Sksewell@umich.edu * property including but not limited to intellectual property relating 82817Sksewell@umich.edu * to a hardware implementation of the functionality of the software 92817Sksewell@umich.edu * licensed hereunder. You may use the software subject to the license 102817Sksewell@umich.edu * terms below provided that you ensure that this notice is replicated 112817Sksewell@umich.edu * unmodified and in its entirety in all distributions of the software, 122817Sksewell@umich.edu * modified or unmodified, in source code or in binary form. 132817Sksewell@umich.edu * 142817Sksewell@umich.edu * Copyright (c) 2002-2005 The Regents of The University of Michigan 152817Sksewell@umich.edu * All rights reserved. 162817Sksewell@umich.edu * 172817Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 182817Sksewell@umich.edu * modification, are permitted provided that the following conditions are 192817Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 202817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 212817Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 222817Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 232817Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 242817Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 252817Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 262817Sksewell@umich.edu * this software without specific prior written permission. 272817Sksewell@umich.edu * 282817Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 294202Sbinkertn@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302817Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312817Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322817Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 334202Sbinkertn@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342817Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 354202Sbinkertn@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 364486Sbinkertn@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 374486Sbinkertn@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 384486Sbinkertn@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 394486Sbinkertn@umich.edu * 404202Sbinkertn@umich.edu * Authors: Ron Dreslinski 414202Sbinkertn@umich.edu * Ali Saidi 424202Sbinkertn@umich.edu * Andreas Hansson 434202Sbinkertn@umich.edu * William Wang 444202Sbinkertn@umich.edu */ 454202Sbinkertn@umich.edu 464202Sbinkertn@umich.edu/** 474202Sbinkertn@umich.edu * @file 484202Sbinkertn@umich.edu * Declaration of an abstract bus base class. 494202Sbinkertn@umich.edu */ 504202Sbinkertn@umich.edu 514202Sbinkertn@umich.edu#ifndef __MEM_BUS_HH__ 524202Sbinkertn@umich.edu#define __MEM_BUS_HH__ 534202Sbinkertn@umich.edu 544202Sbinkertn@umich.edu#include <deque> 554202Sbinkertn@umich.edu 564202Sbinkertn@umich.edu#include "base/addr_range_map.hh" 574202Sbinkertn@umich.edu#include "base/types.hh" 582817Sksewell@umich.edu#include "mem/mem_object.hh" 594202Sbinkertn@umich.edu#include "params/BaseBus.hh" 604202Sbinkertn@umich.edu#include "sim/stats.hh" 614202Sbinkertn@umich.edu 624202Sbinkertn@umich.edu/** 634202Sbinkertn@umich.edu * The base bus contains the common elements of the non-coherent and 644202Sbinkertn@umich.edu * coherent bus. It is an abstract class that does not have any of the 654202Sbinkertn@umich.edu * functionality relating to the actual reception and transmission of 664202Sbinkertn@umich.edu * packets, as this is left for the subclasses. 674202Sbinkertn@umich.edu * 684202Sbinkertn@umich.edu * The BaseBus is responsible for the basic flow control (busy or 694202Sbinkertn@umich.edu * not), the administration of retries, and the address decoding. 704202Sbinkertn@umich.edu */ 714202Sbinkertn@umich.educlass BaseBus : public MemObject 724202Sbinkertn@umich.edu{ 734202Sbinkertn@umich.edu 744202Sbinkertn@umich.edu protected: 754202Sbinkertn@umich.edu 762817Sksewell@umich.edu /** 774202Sbinkertn@umich.edu * A bus layer is an internal bus structure with its own flow 784497Sbinkertn@umich.edu * control and arbitration. Hence, a single-layer bus mimics a 794202Sbinkertn@umich.edu * traditional off-chip tri-state bus (like PCI), where only one 802817Sksewell@umich.edu * set of wires are shared. For on-chip buses, a good starting 814202Sbinkertn@umich.edu * point is to have three layers, for requests, responses, and 824202Sbinkertn@umich.edu * snoop responses respectively (snoop requests are instantaneous 834202Sbinkertn@umich.edu * and do not need any flow control or arbitration). This case is 844202Sbinkertn@umich.edu * similar to AHB and some OCP configurations. 854202Sbinkertn@umich.edu * 862817Sksewell@umich.edu * As a further extensions beyond the three-layer bus, a future 87 * multi-layer bus has with one layer per connected slave port 88 * provides a full or partial crossbar, like AXI, OCP, PCIe etc. 89 * 90 * The template parameter, PortClass, indicates the destination 91 * port type for the bus. The retry list holds either master ports 92 * or slave ports, depending on the direction of the layer. Thus, 93 * a request layer has a retry list containing slave ports, 94 * whereas a response layer holds master ports. 95 */ 96 template <typename SrcType, typename DstType> 97 class Layer : public Drainable 98 { 99 100 public: 101 102 /** 103 * Create a bus layer and give it a name. The bus layer uses 104 * the bus an event manager. 105 * 106 * @param _port destination port the layer converges at 107 * @param _bus the bus this layer belongs to 108 * @param _name the layer's name 109 */ 110 Layer(DstType& _port, BaseBus& _bus, const std::string& _name); 111 112 /** 113 * Drain according to the normal semantics, so that the bus 114 * can tell the layer to drain, and pass an event to signal 115 * back when drained. 116 * 117 * @param de drain event to call once drained 118 * 119 * @return 1 if busy or waiting to retry, or 0 if idle 120 */ 121 unsigned int drain(DrainManager *dm); 122 123 /** 124 * Get the bus layer's name 125 */ 126 const std::string name() const { return bus.name() + _name; } 127 128 129 /** 130 * Determine if the bus layer accepts a packet from a specific 131 * port. If not, the port in question is also added to the 132 * retry list. In either case the state of the layer is 133 * updated accordingly. 134 * 135 * @param port Source port presenting the packet 136 * 137 * @return True if the bus layer accepts the packet 138 */ 139 bool tryTiming(SrcType* src_port); 140 141 /** 142 * Deal with a destination port accepting a packet by potentially 143 * removing the source port from the retry list (if retrying) and 144 * occupying the bus layer accordingly. 145 * 146 * @param busy_time Time to spend as a result of a successful send 147 */ 148 void succeededTiming(Tick busy_time); 149 150 /** 151 * Deal with a destination port not accepting a packet by 152 * potentially adding the source port to the retry list (if 153 * not already at the front) and occupying the bus layer 154 * accordingly. 155 * 156 * @param src_port Source port 157 * @param busy_time Time to spend as a result of a failed send 158 */ 159 void failedTiming(SrcType* src_port, Tick busy_time); 160 161 /** Occupy the bus layer until until */ 162 void occupyLayer(Tick until); 163 164 /** 165 * Send a retry to the port at the head of waitingForLayer. The 166 * caller must ensure that the list is not empty. 167 */ 168 void retryWaiting(); 169 170 /** 171 * Handle a retry from a neighbouring module. This wraps 172 * retryWaiting by verifying that there are ports waiting 173 * before calling retryWaiting. 174 */ 175 void recvRetry(); 176 177 /** 178 * Register stats for the layer 179 */ 180 void regStats(); 181 182 private: 183 184 /** The destination port this layer converges at. */ 185 DstType& port; 186 187 /** The bus this layer is a part of. */ 188 BaseBus& bus; 189 190 /** A name for this layer. */ 191 std::string _name; 192 193 /** 194 * We declare an enum to track the state of the bus layer. The 195 * starting point is an idle state where the bus layer is 196 * waiting for a packet to arrive. Upon arrival, the bus layer 197 * transitions to the busy state, where it remains either 198 * until the packet transfer is done, or the header time is 199 * spent. Once the bus layer leaves the busy state, it can 200 * either go back to idle, if no packets have arrived while it 201 * was busy, or the bus layer goes on to retry the first port 202 * in waitingForLayer. A similar transition takes place from 203 * idle to retry if the bus layer receives a retry from one of 204 * its connected ports. The retry state lasts until the port 205 * in questions calls sendTiming and returns control to the 206 * bus layer, or goes to a busy state if the port does not 207 * immediately react to the retry by calling sendTiming. 208 */ 209 enum State { IDLE, BUSY, RETRY }; 210 211 /** track the state of the bus layer */ 212 State state; 213 214 /** manager to signal when drained */ 215 DrainManager *drainManager; 216 217 /** 218 * A deque of ports that retry should be called on because 219 * the original send was delayed due to a busy layer. 220 */ 221 std::deque<SrcType*> waitingForLayer; 222 223 /** 224 * Port that we are currently in the process of telling to 225 * retry a previously failed attempt to perform a timing 226 * transaction. This is a valid port when in the retry state, 227 * and NULL when in busy or idle. 228 */ 229 SrcType* retryingPort; 230 231 /** 232 * Track who is waiting for the retry when receiving it from a 233 * peer. If no port is waiting NULL is stored. 234 */ 235 SrcType* waitingForPeer; 236 237 /** 238 * Release the bus layer after being occupied and return to an 239 * idle state where we proceed to send a retry to any 240 * potential waiting port, or drain if asked to do so. 241 */ 242 void releaseLayer(); 243 244 /** event used to schedule a release of the layer */ 245 EventWrapper<Layer, &Layer::releaseLayer> releaseEvent; 246 247 /** 248 * Stats for occupancy and utilization. These stats capture 249 * the time the bus spends in the busy state and are thus only 250 * relevant when the memory system is in timing mode. 251 */ 252 Stats::Scalar occupancy; 253 Stats::Formula utilization; 254 255 }; 256 257 /** cycles of overhead per transaction */ 258 const Cycles headerCycles; 259 /** the width of the bus in bytes */ 260 const uint32_t width; 261 262 typedef AddrRangeMap<PortID>::iterator PortMapIter; 263 typedef AddrRangeMap<PortID>::const_iterator PortMapConstIter; 264 AddrRangeMap<PortID> portMap; 265 266 /** all contigous ranges seen by this bus */ 267 AddrRangeList busRanges; 268 269 AddrRange defaultRange; 270 271 /** 272 * Function called by the port when the bus is recieving a range change. 273 * 274 * @param master_port_id id of the port that received the change 275 */ 276 void recvRangeChange(PortID master_port_id); 277 278 /** Find which port connected to this bus (if any) should be given a packet 279 * with this address. 280 * @param addr Address to find port for. 281 * @return id of port that the packet should be sent out of. 282 */ 283 PortID findPort(Addr addr); 284 285 // Cache for the findPort function storing recently used ports from portMap 286 struct PortCache { 287 bool valid; 288 PortID id; 289 AddrRange range; 290 }; 291 292 PortCache portCache[3]; 293 294 // Checks the cache and returns the id of the port that has the requested 295 // address within its range 296 inline PortID checkPortCache(Addr addr) const { 297 if (portCache[0].valid && portCache[0].range.contains(addr)) { 298 return portCache[0].id; 299 } 300 if (portCache[1].valid && portCache[1].range.contains(addr)) { 301 return portCache[1].id; 302 } 303 if (portCache[2].valid && portCache[2].range.contains(addr)) { 304 return portCache[2].id; 305 } 306 307 return InvalidPortID; 308 } 309 310 // Clears the earliest entry of the cache and inserts a new port entry 311 inline void updatePortCache(short id, const AddrRange& range) { 312 portCache[2].valid = portCache[1].valid; 313 portCache[2].id = portCache[1].id; 314 portCache[2].range = portCache[1].range; 315 316 portCache[1].valid = portCache[0].valid; 317 portCache[1].id = portCache[0].id; 318 portCache[1].range = portCache[0].range; 319 320 portCache[0].valid = true; 321 portCache[0].id = id; 322 portCache[0].range = range; 323 } 324 325 // Clears the cache. Needs to be called in constructor. 326 inline void clearPortCache() { 327 portCache[2].valid = false; 328 portCache[1].valid = false; 329 portCache[0].valid = false; 330 } 331 332 /** 333 * Return the address ranges the bus is responsible for. 334 * 335 * @return a list of non-overlapping address ranges 336 */ 337 AddrRangeList getAddrRanges() const; 338 339 /** 340 * Calculate the timing parameters for the packet. Updates the 341 * busFirstWordDelay and busLastWordDelay fields of the packet 342 * object with the relative number of ticks required to transmit 343 * the header and the first word, and the last word, respectively. 344 */ 345 void calcPacketTiming(PacketPtr pkt); 346 347 /** 348 * Ask everyone on the bus what their size is and determine the 349 * bus size as either the maximum, or if no device specifies a 350 * block size return the default. 351 * 352 * @return the max of all the sizes or the default if none is set 353 */ 354 unsigned deviceBlockSize() const; 355 356 /** 357 * Remember for each of the master ports of the bus if we got an 358 * address range from the connected slave. For convenience, also 359 * keep track of if we got ranges from all the slave modules or 360 * not. 361 */ 362 std::vector<bool> gotAddrRanges; 363 bool gotAllAddrRanges; 364 365 /** The master and slave ports of the bus */ 366 std::vector<SlavePort*> slavePorts; 367 std::vector<MasterPort*> masterPorts; 368 369 /** Convenience typedefs. */ 370 typedef std::vector<SlavePort*>::iterator SlavePortIter; 371 typedef std::vector<MasterPort*>::iterator MasterPortIter; 372 typedef std::vector<SlavePort*>::const_iterator SlavePortConstIter; 373 typedef std::vector<MasterPort*>::const_iterator MasterPortConstIter; 374 375 /** Port that handles requests that don't match any of the interfaces.*/ 376 PortID defaultPortID; 377 378 /** If true, use address range provided by default device. Any 379 address not handled by another port and not in default device's 380 range will cause a fatal error. If false, just send all 381 addresses not handled by another port to default device. */ 382 const bool useDefaultRange; 383 384 uint32_t blockSize; 385 386 BaseBus(const BaseBusParams *p); 387 388 virtual ~BaseBus(); 389 390 /** 391 * Stats for transaction distribution and data passing through the 392 * bus. The transaction distribution is globally counting 393 * different types of commands. The packet count and total packet 394 * size are two-dimensional vectors that are indexed by the bus 395 * slave port and master port id (thus the neighbouring master and 396 * neighbouring slave), summing up both directions (request and 397 * response). 398 */ 399 Stats::Formula throughput; 400 Stats::Vector transDist; 401 Stats::Vector2d pktCount; 402 Stats::Vector2d totPktSize; 403 404 public: 405 406 virtual void init(); 407 408 /** A function used to return the port associated with this bus object. */ 409 BaseMasterPort& getMasterPort(const std::string& if_name, 410 PortID idx = InvalidPortID); 411 BaseSlavePort& getSlavePort(const std::string& if_name, 412 PortID idx = InvalidPortID); 413 414 virtual unsigned int drain(DrainManager *dm) = 0; 415 416 virtual void regStats(); 417 418}; 419 420#endif //__MEM_BUS_HH__ 421