xbar.hh revision 9091 
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 *          Ali Saidi
42 *          Andreas Hansson
43 *          William Wang
44 */
45
46/**
47 * @file
48 * Declaration of an abstract bus base class.
49 */
50
51#ifndef __MEM_BUS_HH__
52#define __MEM_BUS_HH__
53
54#include <list>
55#include <set>
56
57#include "base/range.hh"
58#include "base/range_map.hh"
59#include "base/types.hh"
60#include "mem/mem_object.hh"
61#include "params/BaseBus.hh"
62
63/**
64 * The base bus contains the common elements of the non-coherent and
65 * coherent bus. It is an abstract class that does not have any of the
66 * functionality relating to the actual reception and transmission of
67 * packets, as this is left for the subclasses.
68 *
69 * The BaseBus is responsible for the basic flow control (busy or
70 * not), the administration of retries, and the address decoding.
71 */
72class BaseBus : public MemObject
73{
74
75  protected:
76
77    /**
78     * We declare an enum to track the state of the bus. The starting
79     * point is an idle state where the bus is waiting for a packet to
80     * arrive. Upon arrival, the bus transitions to the busy state,
81     * where it remains either until the packet transfer is done, or
82     * the header time is spent. Once the bus leaves the busy state,
83     * it can either go back to idle, if no packets have arrived while
84     * it was busy, or the bus goes on to retry the first port on the
85     * retryList. A similar transition takes place from idle to retry
86     * if the bus receives a retry from one of its connected
87     * ports. The retry state lasts until the port in questions calls
88     * sendTiming and returns control to the bus, or goes to a busy
89     * state if the port does not immediately react to the retry by
90     * calling sendTiming.
91     */
92    enum State { IDLE, BUSY, RETRY };
93
94    /** track the state of the bus */
95    State state;
96
97    /** the clock speed for the bus */
98    int clock;
99    /** cycles of overhead per transaction */
100    int headerCycles;
101    /** the width of the bus in bytes */
102    int width;
103
104    Event * drainEvent;
105
106    typedef range_map<Addr, PortID>::iterator PortMapIter;
107    typedef range_map<Addr, PortID>::const_iterator PortMapConstIter;
108    range_map<Addr, PortID> portMap;
109
110    AddrRangeList defaultRange;
111
112    /**
113     * Determine if the bus accepts a packet from a specific port. If
114     * not, the port in question is also added to the retry list. In
115     * either case the state of the bus is updated accordingly.
116     *
117     * @param port Source port on the bus presenting the packet
118     *
119     * @return True if the bus accepts the packet
120     */
121    bool tryTiming(Port* port);
122
123    /**
124     * Deal with a destination port accepting a packet by potentially
125     * removing the source port from the retry list (if retrying) and
126     * occupying the bus accordingly.
127     *
128     * @param busy_time Time to spend as a result of a successful send
129     */
130    void succeededTiming(Tick busy_time);
131
132    /**
133     * Deal with a destination port not accepting a packet by
134     * potentially adding the source port to the retry list (if
135     * not already at the front) and occupying the bus accordingly.
136     *
137     * @param busy_time Time to spend as a result of a failed send
138     */
139    void failedTiming(SlavePort* port, Tick busy_time);
140
141    /** Timing function called by port when it is once again able to process
142     * requests. */
143    void recvRetry();
144
145    /**
146     * Function called by the port when the bus is recieving a range change.
147     *
148     * @param master_port_id id of the port that received the change
149     */
150    void recvRangeChange(PortID master_port_id);
151
152    /** Find which port connected to this bus (if any) should be given a packet
153     * with this address.
154     * @param addr Address to find port for.
155     * @return id of port that the packet should be sent out of.
156     */
157    PortID findPort(Addr addr);
158
159    // Cache for the findPort function storing recently used ports from portMap
160    struct PortCache {
161        bool valid;
162        PortID id;
163        Addr start;
164        Addr end;
165    };
166
167    PortCache portCache[3];
168
169    // Checks the cache and returns the id of the port that has the requested
170    // address within its range
171    inline PortID checkPortCache(Addr addr) {
172        if (portCache[0].valid && addr >= portCache[0].start &&
173            addr < portCache[0].end) {
174            return portCache[0].id;
175        }
176        if (portCache[1].valid && addr >= portCache[1].start &&
177                   addr < portCache[1].end) {
178            return portCache[1].id;
179        }
180        if (portCache[2].valid && addr >= portCache[2].start &&
181            addr < portCache[2].end) {
182            return portCache[2].id;
183        }
184
185        return InvalidPortID;
186    }
187
188    // Clears the earliest entry of the cache and inserts a new port entry
189    inline void updatePortCache(short id, Addr start, Addr end) {
190        portCache[2].valid = portCache[1].valid;
191        portCache[2].id    = portCache[1].id;
192        portCache[2].start = portCache[1].start;
193        portCache[2].end   = portCache[1].end;
194
195        portCache[1].valid = portCache[0].valid;
196        portCache[1].id    = portCache[0].id;
197        portCache[1].start = portCache[0].start;
198        portCache[1].end   = portCache[0].end;
199
200        portCache[0].valid = true;
201        portCache[0].id    = id;
202        portCache[0].start = start;
203        portCache[0].end   = end;
204    }
205
206    // Clears the cache. Needs to be called in constructor.
207    inline void clearPortCache() {
208        portCache[2].valid = false;
209        portCache[1].valid = false;
210        portCache[0].valid = false;
211    }
212
213    /**
214     * Return the address ranges the bus is responsible for.
215     *
216     * @return a list of non-overlapping address ranges
217     */
218    AddrRangeList getAddrRanges() const;
219
220    /** Calculate the timing parameters for the packet.  Updates the
221     * firstWordTime and finishTime fields of the packet object.
222     * Returns the tick at which the packet header is completed (which
223     * will be all that is sent if the target rejects the packet).
224     */
225    Tick calcPacketTiming(PacketPtr pkt);
226
227    /** Occupy the bus until until */
228    void occupyBus(Tick until);
229
230    /**
231     * Release the bus after being occupied and return to an idle
232     * state where we proceed to send a retry to any potential waiting
233     * port, or drain if asked to do so.
234     */
235    void releaseBus();
236
237    /**
238     * Send a retry to the port at the head of the retryList. The
239     * caller must ensure that the list is not empty.
240     */
241    void retryWaiting();
242
243    /**
244     * Ask everyone on the bus what their size is
245     *
246     * @return the max of all the sizes
247     */
248    unsigned findBlockSize();
249
250    // event used to schedule a release of the bus
251    EventWrapper<BaseBus, &BaseBus::releaseBus> busIdleEvent;
252
253    std::set<PortID> inRecvRangeChange;
254
255    /** The master and slave ports of the bus */
256    std::vector<SlavePort*> slavePorts;
257    std::vector<MasterPort*> masterPorts;
258
259    /** Convenience typedefs. */
260    typedef std::vector<SlavePort*>::iterator SlavePortIter;
261    typedef std::vector<MasterPort*>::iterator MasterPortIter;
262    typedef std::vector<SlavePort*>::const_iterator SlavePortConstIter;
263    typedef std::vector<MasterPort*>::const_iterator MasterPortConstIter;
264
265    /** An array of pointers to ports that retry should be called on because the
266     * original send failed for whatever reason.*/
267    std::list<Port*> retryList;
268
269    /** Port that handles requests that don't match any of the interfaces.*/
270    PortID defaultPortID;
271
272    /** If true, use address range provided by default device.  Any
273       address not handled by another port and not in default device's
274       range will cause a fatal error.  If false, just send all
275       addresses not handled by another port to default device. */
276    bool useDefaultRange;
277
278    unsigned defaultBlockSize;
279    unsigned cachedBlockSize;
280    bool cachedBlockSizeValid;
281
282    BaseBus(const BaseBusParams *p);
283
284    virtual ~BaseBus();
285
286  public:
287
288    /** A function used to return the port associated with this bus object. */
289    virtual MasterPort& getMasterPort(const std::string& if_name, int idx = -1);
290    virtual SlavePort& getSlavePort(const std::string& if_name, int idx = -1);
291
292    unsigned int drain(Event *de);
293
294};
295
296#endif //__MEM_BUS_HH__
297