xbar.cc revision 2565
17404SAli.Saidi@ARM.com/*
27404SAli.Saidi@ARM.com * Copyright (c) 2006 The Regents of The University of Michigan
37404SAli.Saidi@ARM.com * All rights reserved.
47404SAli.Saidi@ARM.com *
57404SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without
67404SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are
77404SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright
87404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer;
97404SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright
107404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the
117404SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution;
127404SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its
137404SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from
147404SAli.Saidi@ARM.com * this software without specific prior written permission.
157404SAli.Saidi@ARM.com *
167404SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
177404SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
187404SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
197404SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
207404SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
217404SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
227404SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
237404SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
247404SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
257404SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
267404SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
277404SAli.Saidi@ARM.com */
287404SAli.Saidi@ARM.com
297404SAli.Saidi@ARM.com/**
307404SAli.Saidi@ARM.com * @file Definition of a bus object.
317404SAli.Saidi@ARM.com */
327404SAli.Saidi@ARM.com
337404SAli.Saidi@ARM.com
347404SAli.Saidi@ARM.com#include "base/trace.hh"
357404SAli.Saidi@ARM.com#include "mem/bus.hh"
367404SAli.Saidi@ARM.com#include "sim/builder.hh"
377404SAli.Saidi@ARM.com
387404SAli.Saidi@ARM.com/** Function called by the port when the bus is recieving a Timing
397404SAli.Saidi@ARM.com * transaction.*/
407404SAli.Saidi@ARM.combool
417404SAli.Saidi@ARM.comBus::recvTiming(Packet &pkt, int id)
427404SAli.Saidi@ARM.com{
437728SAli.Saidi@ARM.com
447404SAli.Saidi@ARM.com    panic("I need to be implemented, but not right now.");
458245Snate@binkert.org}
468245Snate@binkert.org
478245Snate@binkert.orgPort *
488229Snate@binkert.orgBus::findPort(Addr addr, int id)
497748SAli.Saidi@ARM.com{
507404SAli.Saidi@ARM.com    /* An interval tree would be a better way to do this. --ali. */
517404SAli.Saidi@ARM.com    int dest_id = -1;
527404SAli.Saidi@ARM.com    int i = 0;
537404SAli.Saidi@ARM.com    bool found = false;
547728SAli.Saidi@ARM.com
557728SAli.Saidi@ARM.com    while (i < portList.size() && !found)
567439Sdam.sunwoo@arm.com    {
577576SAli.Saidi@ARM.com        if (portList[i].range == addr) {
587439Sdam.sunwoo@arm.com            dest_id = portList[i].portId;
597404SAli.Saidi@ARM.com            found = true;
607404SAli.Saidi@ARM.com            DPRINTF(Bus, "Found Addr: %llx on device %d\n", addr, dest_id);
617404SAli.Saidi@ARM.com        }
627404SAli.Saidi@ARM.com        i++;
637404SAli.Saidi@ARM.com    }
647404SAli.Saidi@ARM.com    if (dest_id == -1)
657404SAli.Saidi@ARM.com        panic("Unable to find destination for addr: %llx", addr);
667748SAli.Saidi@ARM.com
677748SAli.Saidi@ARM.com    // we shouldn't be sending this back to where it came from
687404SAli.Saidi@ARM.com    assert(dest_id != id);
697748SAli.Saidi@ARM.com
707733SAli.Saidi@ARM.com    return interfaces[dest_id];
717733SAli.Saidi@ARM.com}
727733SAli.Saidi@ARM.com
737733SAli.Saidi@ARM.com/** Function called by the port when the bus is recieving a Atomic
747733SAli.Saidi@ARM.com * transaction.*/
757733SAli.Saidi@ARM.comTick
767733SAli.Saidi@ARM.comBus::recvAtomic(Packet &pkt, int id)
777733SAli.Saidi@ARM.com{
787733SAli.Saidi@ARM.com    return findPort(pkt.addr, id)->sendAtomic(pkt);
797733SAli.Saidi@ARM.com}
807733SAli.Saidi@ARM.com
817404SAli.Saidi@ARM.com/** Function called by the port when the bus is recieving a Functional
827404SAli.Saidi@ARM.com * transaction.*/
837748SAli.Saidi@ARM.comvoid
847748SAli.Saidi@ARM.comBus::recvFunctional(Packet &pkt, int id)
857748SAli.Saidi@ARM.com{
867748SAli.Saidi@ARM.com    findPort(pkt.addr, id)->sendFunctional(pkt);
877748SAli.Saidi@ARM.com}
887748SAli.Saidi@ARM.com
897748SAli.Saidi@ARM.com/** Function called by the port when the bus is recieving a status change.*/
907748SAli.Saidi@ARM.comvoid
917748SAli.Saidi@ARM.comBus::recvStatusChange(Port::Status status, int id)
927748SAli.Saidi@ARM.com{
937404SAli.Saidi@ARM.com    assert(status == Port::RangeChange &&
947404SAli.Saidi@ARM.com           "The other statuses need to be implemented.");
957404SAli.Saidi@ARM.com
967404SAli.Saidi@ARM.com    assert(id < interfaces.size() && id >= 0);
977404SAli.Saidi@ARM.com    Port *port = interfaces[id];
987781SAli.Saidi@ARM.com    AddrRangeList ranges;
997404SAli.Saidi@ARM.com    AddrRangeList snoops;
1007404SAli.Saidi@ARM.com    AddrRangeIter iter;
1017404SAli.Saidi@ARM.com    std::vector<DevMap>::iterator portIter;
1027404SAli.Saidi@ARM.com
1037404SAli.Saidi@ARM.com    // Clean out any previously existent ids
1047404SAli.Saidi@ARM.com    for (portIter = portList.begin(); portIter != portList.end(); ) {
1057404SAli.Saidi@ARM.com        if (portIter->portId == id)
1067404SAli.Saidi@ARM.com            portIter = portList.erase(portIter);
1077404SAli.Saidi@ARM.com        else
1087404SAli.Saidi@ARM.com            portIter++;
1097437Sdam.sunwoo@arm.com    }
1107404SAli.Saidi@ARM.com
1117404SAli.Saidi@ARM.com    port->getPeerAddressRanges(ranges, snoops);
1127439Sdam.sunwoo@arm.com
1137439Sdam.sunwoo@arm.com    // not dealing with snooping yet either
1147439Sdam.sunwoo@arm.com    assert(snoops.size() == 0);
1157439Sdam.sunwoo@arm.com    for(iter = ranges.begin(); iter != ranges.end(); iter++) {
1167439Sdam.sunwoo@arm.com        DevMap dm;
1177404SAli.Saidi@ARM.com        dm.portId = id;
1187439Sdam.sunwoo@arm.com        dm.range = *iter;
1197439Sdam.sunwoo@arm.com
1208202SAli.Saidi@ARM.com        DPRINTF(MMU, "Adding range %llx - %llx for id %d\n", dm.range.start,
1218202SAli.Saidi@ARM.com                dm.range.end, id);
1228202SAli.Saidi@ARM.com        portList.push_back(dm);
1238202SAli.Saidi@ARM.com    }
1248202SAli.Saidi@ARM.com    DPRINTF(MMU, "port list has %d entries\n", portList.size());
1258202SAli.Saidi@ARM.com}
1268202SAli.Saidi@ARM.com
1278202SAli.Saidi@ARM.comvoid
1288202SAli.Saidi@ARM.comBus::BusPort::addressRanges(AddrRangeList &resp, AddrRangeList &snoop)
1298202SAli.Saidi@ARM.com{
1307439Sdam.sunwoo@arm.com    panic("I'm not implemented.\n");
1317439Sdam.sunwoo@arm.com}
1327439Sdam.sunwoo@arm.com
1337439Sdam.sunwoo@arm.comBEGIN_DECLARE_SIM_OBJECT_PARAMS(Bus)
1347439Sdam.sunwoo@arm.com
1357439Sdam.sunwoo@arm.com    Param<int> bus_id;
1367439Sdam.sunwoo@arm.com
1377439Sdam.sunwoo@arm.comEND_DECLARE_SIM_OBJECT_PARAMS(Bus)
1387439Sdam.sunwoo@arm.com
1397439Sdam.sunwoo@arm.comBEGIN_INIT_SIM_OBJECT_PARAMS(Bus)
1407404SAli.Saidi@ARM.com    INIT_PARAM(bus_id, "junk bus id")
1417436Sdam.sunwoo@arm.comEND_INIT_SIM_OBJECT_PARAMS(PhysicalMemory)
1427436Sdam.sunwoo@arm.com
1437720Sgblack@eecs.umich.eduCREATE_SIM_OBJECT(Bus)
1447439Sdam.sunwoo@arm.com{
1457439Sdam.sunwoo@arm.com    return new Bus(getInstanceName());
1467439Sdam.sunwoo@arm.com}
1477439Sdam.sunwoo@arm.com
1487439Sdam.sunwoo@arm.comREGISTER_SIM_OBJECT("Bus", Bus)
1497439Sdam.sunwoo@arm.com