tport.hh revision 9063 
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 *          Andreas Hansson
42 */
43
44#ifndef __MEM_TPORT_HH__
45#define __MEM_TPORT_HH__
46
47/**
48 * @file
49 *
50 * Declaration of SimpleTimingPort.
51 */
52
53#include "mem/qport.hh"
54
55/**
56 * The simple timing port uses a queued port to implement
57 * recvFunctional and recvTimingReq through recvAtomic. It is always a
58 * slave port.
59 */
60class SimpleTimingPort : public QueuedSlavePort
61{
62
63  protected:
64
65    /** The packet queue used to store outgoing responses. */
66    SlavePacketQueue queue;
67
68    /** Implemented using recvAtomic(). */
69    void recvFunctional(PacketPtr pkt);
70
71    /** Implemented using recvAtomic(). */
72    bool recvTimingReq(PacketPtr pkt);
73
74    virtual Tick recvAtomic(PacketPtr pkt) = 0;
75
76    /**
77     * @todo this is a temporary workaround until the 4-phase code is committed.
78     * upstream caches need this packet until true is returned, so hold it for
79     * deletion until a subsequent call
80     */
81    std::vector<PacketPtr> pendingDelete;
82
83
84  public:
85
86    /**
87     * Create a new SimpleTimingPort that relies on a packet queue to
88     * hold responses, and implements recvTimingReq and recvFunctional
89     * through calls to recvAtomic. Once a request arrives, it is
90     * passed to recvAtomic, and in the case of a timing access any
91     * response is scheduled to be sent after the delay of the atomic
92     * operation.
93     *
94     * @param name port name
95     * @param owner structural owner
96     */
97    SimpleTimingPort(const std::string& name, MemObject* owner);
98
99    virtual ~SimpleTimingPort() { }
100
101};
102
103#endif // __MEM_TPORT_HH__
104