tport.hh revision 9097
19651SAndreas.Sandberg@ARM.com/* 29651SAndreas.Sandberg@ARM.com * Copyright (c) 2012 ARM Limited 39651SAndreas.Sandberg@ARM.com * All rights reserved. 49651SAndreas.Sandberg@ARM.com * 59651SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 69651SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 79651SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 89651SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 99651SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 109651SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 119651SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 129651SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 139651SAndreas.Sandberg@ARM.com * 149651SAndreas.Sandberg@ARM.com * Copyright (c) 2006 The Regents of The University of Michigan 159651SAndreas.Sandberg@ARM.com * All rights reserved. 169651SAndreas.Sandberg@ARM.com * 179651SAndreas.Sandberg@ARM.com * Redistribution and use in source and binary forms, with or without 189651SAndreas.Sandberg@ARM.com * modification, are permitted provided that the following conditions are 199651SAndreas.Sandberg@ARM.com * met: redistributions of source code must retain the above copyright 209651SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer; 219651SAndreas.Sandberg@ARM.com * redistributions in binary form must reproduce the above copyright 229651SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer in the 239651SAndreas.Sandberg@ARM.com * documentation and/or other materials provided with the distribution; 249651SAndreas.Sandberg@ARM.com * neither the name of the copyright holders nor the names of its 259651SAndreas.Sandberg@ARM.com * contributors may be used to endorse or promote products derived from 269651SAndreas.Sandberg@ARM.com * this software without specific prior written permission. 279651SAndreas.Sandberg@ARM.com * 289651SAndreas.Sandberg@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299651SAndreas.Sandberg@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309651SAndreas.Sandberg@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319651SAndreas.Sandberg@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329651SAndreas.Sandberg@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339651SAndreas.Sandberg@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349651SAndreas.Sandberg@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359651SAndreas.Sandberg@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369651SAndreas.Sandberg@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379651SAndreas.Sandberg@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389651SAndreas.Sandberg@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399651SAndreas.Sandberg@ARM.com * 409651SAndreas.Sandberg@ARM.com * Authors: Ali Saidi 419651SAndreas.Sandberg@ARM.com * Andreas Hansson 429651SAndreas.Sandberg@ARM.com */ 439651SAndreas.Sandberg@ARM.com 449651SAndreas.Sandberg@ARM.com#ifndef __MEM_TPORT_HH__ 459651SAndreas.Sandberg@ARM.com#define __MEM_TPORT_HH__ 469651SAndreas.Sandberg@ARM.com 479651SAndreas.Sandberg@ARM.com/** 489651SAndreas.Sandberg@ARM.com * @file 499651SAndreas.Sandberg@ARM.com * 509651SAndreas.Sandberg@ARM.com * Declaration of SimpleTimingPort. 519651SAndreas.Sandberg@ARM.com */ 529651SAndreas.Sandberg@ARM.com 539651SAndreas.Sandberg@ARM.com#include "mem/qport.hh" 549651SAndreas.Sandberg@ARM.com 559651SAndreas.Sandberg@ARM.com/** 569651SAndreas.Sandberg@ARM.com * The simple timing port uses a queued port to implement 579651SAndreas.Sandberg@ARM.com * recvFunctional and recvTimingReq through recvAtomic. It is always a 589651SAndreas.Sandberg@ARM.com * slave port. 599651SAndreas.Sandberg@ARM.com */ 609651SAndreas.Sandberg@ARM.comclass SimpleTimingPort : public QueuedSlavePort 619651SAndreas.Sandberg@ARM.com{ 629651SAndreas.Sandberg@ARM.com 639651SAndreas.Sandberg@ARM.com private: 649651SAndreas.Sandberg@ARM.com 659651SAndreas.Sandberg@ARM.com /** 669651SAndreas.Sandberg@ARM.com * The packet queue used to store outgoing responses. Note that 679651SAndreas.Sandberg@ARM.com * the queue is made private and that we avoid overloading the 689651SAndreas.Sandberg@ARM.com * name used in the QueuedSlavePort. Access is provided through 699651SAndreas.Sandberg@ARM.com * the queue reference in the base class. 709651SAndreas.Sandberg@ARM.com */ 719651SAndreas.Sandberg@ARM.com SlavePacketQueue queueImpl; 729651SAndreas.Sandberg@ARM.com 739651SAndreas.Sandberg@ARM.com protected: 749651SAndreas.Sandberg@ARM.com 759651SAndreas.Sandberg@ARM.com /** Implemented using recvAtomic(). */ 769651SAndreas.Sandberg@ARM.com void recvFunctional(PacketPtr pkt); 779651SAndreas.Sandberg@ARM.com 789651SAndreas.Sandberg@ARM.com /** Implemented using recvAtomic(). */ 799651SAndreas.Sandberg@ARM.com bool recvTimingReq(PacketPtr pkt); 809651SAndreas.Sandberg@ARM.com 819651SAndreas.Sandberg@ARM.com virtual Tick recvAtomic(PacketPtr pkt) = 0; 829651SAndreas.Sandberg@ARM.com 839651SAndreas.Sandberg@ARM.com /** 849651SAndreas.Sandberg@ARM.com * @todo this is a temporary workaround until the 4-phase code is committed. 859651SAndreas.Sandberg@ARM.com * upstream caches need this packet until true is returned, so hold it for 869651SAndreas.Sandberg@ARM.com * deletion until a subsequent call 879651SAndreas.Sandberg@ARM.com */ 889651SAndreas.Sandberg@ARM.com std::vector<PacketPtr> pendingDelete; 899651SAndreas.Sandberg@ARM.com 909651SAndreas.Sandberg@ARM.com 919651SAndreas.Sandberg@ARM.com public: 929651SAndreas.Sandberg@ARM.com 939651SAndreas.Sandberg@ARM.com /** 949651SAndreas.Sandberg@ARM.com * Create a new SimpleTimingPort that relies on a packet queue to 959651SAndreas.Sandberg@ARM.com * hold responses, and implements recvTimingReq and recvFunctional 969688Sandreas@sandberg.pp.se * through calls to recvAtomic. Once a request arrives, it is 979688Sandreas@sandberg.pp.se * passed to recvAtomic, and in the case of a timing access any 989651SAndreas.Sandberg@ARM.com * response is scheduled to be sent after the delay of the atomic 999651SAndreas.Sandberg@ARM.com * operation. 1009651SAndreas.Sandberg@ARM.com * 1019651SAndreas.Sandberg@ARM.com * @param name port name 1029651SAndreas.Sandberg@ARM.com * @param owner structural owner 1039651SAndreas.Sandberg@ARM.com */ 1049651SAndreas.Sandberg@ARM.com SimpleTimingPort(const std::string& name, MemObject* owner); 1059652SAndreas.Sandberg@ARM.com 1069652SAndreas.Sandberg@ARM.com virtual ~SimpleTimingPort() { } 1079651SAndreas.Sandberg@ARM.com 1089651SAndreas.Sandberg@ARM.com}; 1099651SAndreas.Sandberg@ARM.com 1109651SAndreas.Sandberg@ARM.com#endif // __MEM_TPORT_HH__ 1119651SAndreas.Sandberg@ARM.com