tport.cc revision 8856
1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 * Andreas Hansson 42 */ 43 44#include "debug/Bus.hh" 45#include "mem/mem_object.hh" 46#include "mem/tport.hh" 47 48using namespace std; 49 50SimpleTimingPort::SimpleTimingPort(const string &_name, MemObject *_owner, 51 const string _label) 52 : Port(_name, _owner), label(_label), sendEvent(this), drainEvent(NULL), 53 waitingOnRetry(false) 54{ 55} 56 57SimpleTimingPort::~SimpleTimingPort() 58{ 59} 60 61bool 62SimpleTimingPort::checkFunctional(PacketPtr pkt) 63{ 64 pkt->pushLabel(label); 65 66 DeferredPacketIterator i = transmitList.begin(); 67 DeferredPacketIterator end = transmitList.end(); 68 bool found = false; 69 70 while (!found && i != end) { 71 // If the buffered packet contains data, and it overlaps the 72 // current packet, then update data 73 found = pkt->checkFunctional(i->pkt); 74 ++i; 75 } 76 77 pkt->popLabel(); 78 79 return found; 80} 81 82void 83SimpleTimingPort::recvFunctional(PacketPtr pkt) 84{ 85 if (!checkFunctional(pkt)) { 86 // Just do an atomic access and throw away the returned latency 87 recvAtomic(pkt); 88 } 89} 90 91bool 92SimpleTimingPort::recvTiming(PacketPtr pkt) 93{ 94 // If the device is only a slave, it should only be sending 95 // responses, which should never get nacked. There used to be 96 // code to hanldle nacks here, but I'm pretty sure it didn't work 97 // correctly with the drain code, so that would need to be fixed 98 // if we ever added it back. 99 100 if (pkt->memInhibitAsserted()) { 101 // snooper will supply based on copy of packet 102 // still target's responsibility to delete packet 103 delete pkt; 104 return true; 105 } 106 107 bool needsResponse = pkt->needsResponse(); 108 Tick latency = recvAtomic(pkt); 109 // turn packet around to go back to requester if response expected 110 if (needsResponse) { 111 // recvAtomic() should already have turned packet into 112 // atomic response 113 assert(pkt->isResponse()); 114 schedSendTiming(pkt, curTick() + latency); 115 } else { 116 delete pkt; 117 } 118 119 return true; 120} 121 122void 123SimpleTimingPort::schedSendEvent(Tick when) 124{ 125 // if we are waiting on a retry, do not schedule a send event, and 126 // instead rely on retry being called 127 if (waitingOnRetry) { 128 assert(!sendEvent.scheduled()); 129 return; 130 } 131 132 if (!sendEvent.scheduled()) { 133 owner->schedule(&sendEvent, when); 134 } else if (sendEvent.when() > when) { 135 owner->reschedule(&sendEvent, when); 136 } 137} 138 139void 140SimpleTimingPort::schedSendTiming(PacketPtr pkt, Tick when) 141{ 142 assert(when > curTick()); 143 assert(when < curTick() + SimClock::Int::ms); 144 145 // Nothing is on the list: add it and schedule an event 146 if (transmitList.empty() || when < transmitList.front().tick) { 147 transmitList.push_front(DeferredPacket(when, pkt)); 148 schedSendEvent(when); 149 return; 150 } 151 152 // list is non-empty & this belongs at the end 153 if (when >= transmitList.back().tick) { 154 transmitList.push_back(DeferredPacket(when, pkt)); 155 return; 156 } 157 158 // this belongs in the middle somewhere 159 DeferredPacketIterator i = transmitList.begin(); 160 i++; // already checked for insertion at front 161 DeferredPacketIterator end = transmitList.end(); 162 163 for (; i != end; ++i) { 164 if (when < i->tick) { 165 transmitList.insert(i, DeferredPacket(when, pkt)); 166 return; 167 } 168 } 169 assert(false); // should never get here 170} 171 172void SimpleTimingPort::trySendTiming() 173{ 174 assert(deferredPacketReady()); 175 // take the next packet off the list here, as we might return to 176 // ourselves through the sendTiming call below 177 DeferredPacket dp = transmitList.front(); 178 transmitList.pop_front(); 179 180 // attempt to send the packet and remember the outcome 181 waitingOnRetry = !sendTiming(dp.pkt); 182 183 if (waitingOnRetry) { 184 // put the packet back at the front of the list (packet should 185 // not have changed since it wasn't accepted) 186 assert(!sendEvent.scheduled()); 187 transmitList.push_front(dp); 188 } 189} 190 191void 192SimpleTimingPort::scheduleSend(Tick time) 193{ 194 // the next ready time is either determined by the next deferred packet, 195 // or in the cache through the MSHR ready time 196 Tick nextReady = std::min(deferredPacketReadyTime(), time); 197 if (nextReady != MaxTick) { 198 // if the sendTiming caused someone else to call our 199 // recvTiming we could already have an event scheduled, check 200 if (!sendEvent.scheduled()) 201 owner->schedule(&sendEvent, std::max(nextReady, curTick() + 1)); 202 } else { 203 // no more to send, so if we're draining, we may be done 204 if (drainEvent && !sendEvent.scheduled()) { 205 drainEvent->process(); 206 drainEvent = NULL; 207 } 208 } 209} 210 211void 212SimpleTimingPort::sendDeferredPacket() 213{ 214 // try to send what is on the list 215 trySendTiming(); 216 217 // if we succeeded and are not waiting for a retry, schedule the 218 // next send 219 if (!waitingOnRetry) { 220 scheduleSend(); 221 } 222} 223 224 225void 226SimpleTimingPort::recvRetry() 227{ 228 DPRINTF(Bus, "Received retry\n"); 229 // note that in the cache we get a retry even though we may not 230 // have a packet to retry (we could potentially decide on a new 231 // packet every time we retry) 232 assert(waitingOnRetry); 233 sendDeferredPacket(); 234} 235 236 237void 238SimpleTimingPort::processSendEvent() 239{ 240 assert(!waitingOnRetry); 241 sendDeferredPacket(); 242} 243 244 245unsigned int 246SimpleTimingPort::drain(Event *de) 247{ 248 if (transmitList.empty() && !sendEvent.scheduled()) 249 return 0; 250 drainEvent = de; 251 return 1; 252} 253