tport.cc revision 8708
12623SN/A/* 27725SAli.Saidi@ARM.com * Copyright (c) 2006 The Regents of The University of Michigan 37725SAli.Saidi@ARM.com * All rights reserved. 47725SAli.Saidi@ARM.com * 57725SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 67725SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 77725SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 87725SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 97725SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 107725SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 117725SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 127725SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 137725SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272623SN/A * 282623SN/A * Authors: Ali Saidi 292623SN/A */ 302623SN/A 312623SN/A#include "debug/Bus.hh" 322623SN/A#include "mem/mem_object.hh" 332623SN/A#include "mem/tport.hh" 342623SN/A 352623SN/Ausing namespace std; 362623SN/A 372623SN/ASimpleTimingPort::SimpleTimingPort(string pname, MemObject *_owner) 382623SN/A : Port(pname, _owner), sendEvent(NULL), drainEvent(NULL), 392665Ssaidi@eecs.umich.edu waitingOnRetry(false) 402665Ssaidi@eecs.umich.edu{ 412623SN/A sendEvent = new EventWrapper<SimpleTimingPort, 422623SN/A &SimpleTimingPort::processSendEvent>(this); 433170Sstever@eecs.umich.edu} 445103Ssaidi@eecs.umich.edu 452623SN/ASimpleTimingPort::~SimpleTimingPort() 464040Ssaidi@eecs.umich.edu{ 476658Snate@binkert.org delete sendEvent; 482623SN/A} 492623SN/A 503348Sbinkertn@umich.edubool 513348Sbinkertn@umich.eduSimpleTimingPort::checkFunctional(PacketPtr pkt) 524762Snate@binkert.org{ 537678Sgblack@eecs.umich.edu DeferredPacketIterator i = transmitList.begin(); 542901Ssaidi@eecs.umich.edu DeferredPacketIterator end = transmitList.end(); 552623SN/A 562623SN/A for (; i != end; ++i) { 572623SN/A PacketPtr target = i->pkt; 582623SN/A // If the target contains data, and it overlaps the 592856Srdreslin@umich.edu // probed request, need to update data 602856Srdreslin@umich.edu if (pkt->checkFunctional(target)) { 612856Srdreslin@umich.edu return true; 622856Srdreslin@umich.edu } 632856Srdreslin@umich.edu } 642856Srdreslin@umich.edu 652856Srdreslin@umich.edu return false; 662856Srdreslin@umich.edu} 672856Srdreslin@umich.edu 682856Srdreslin@umich.eduvoid 692623SN/ASimpleTimingPort::recvFunctional(PacketPtr pkt) 702623SN/A{ 712623SN/A if (!checkFunctional(pkt)) { 722623SN/A // Just do an atomic access and throw away the returned latency 732623SN/A recvAtomic(pkt); 742623SN/A } 752680Sktlim@umich.edu} 762680Sktlim@umich.edu 772623SN/Abool 782623SN/ASimpleTimingPort::recvTiming(PacketPtr pkt) 795712Shsul@eecs.umich.edu{ 802623SN/A // If the device is only a slave, it should only be sending 812623SN/A // responses, which should never get nacked. There used to be 822623SN/A // code to hanldle nacks here, but I'm pretty sure it didn't work 832623SN/A // correctly with the drain code, so that would need to be fixed 842623SN/A // if we ever added it back. 853349Sbinkertn@umich.edu 862623SN/A if (pkt->memInhibitAsserted()) { 872623SN/A // snooper will supply based on copy of packet 887823Ssteve.reinhardt@amd.com // still target's responsibility to delete packet 892623SN/A delete pkt; 902623SN/A return true; 912623SN/A } 923349Sbinkertn@umich.edu 932623SN/A bool needsResponse = pkt->needsResponse(); 943184Srdreslin@umich.edu Tick latency = recvAtomic(pkt); 953184Srdreslin@umich.edu // turn packet around to go back to requester if response expected 962623SN/A if (needsResponse) { 972623SN/A // recvAtomic() should already have turned packet into 982623SN/A // atomic response 992623SN/A assert(pkt->isResponse()); 1002623SN/A schedSendTiming(pkt, curTick() + latency); 1013647Srdreslin@umich.edu } else { 1023647Srdreslin@umich.edu delete pkt; 1033647Srdreslin@umich.edu } 1043647Srdreslin@umich.edu 1053647Srdreslin@umich.edu return true; 1062631SN/A} 1073647Srdreslin@umich.edu 1082631SN/Avoid 1092623SN/ASimpleTimingPort::schedSendEvent(Tick when) 1102623SN/A{ 1112623SN/A if (waitingOnRetry) { 1122948Ssaidi@eecs.umich.edu assert(!sendEvent->scheduled()); 1132948Ssaidi@eecs.umich.edu return; 1143349Sbinkertn@umich.edu } 1152948Ssaidi@eecs.umich.edu 1162948Ssaidi@eecs.umich.edu if (!sendEvent->scheduled()) { 1175606Snate@binkert.org owner->schedule(sendEvent, when); 1182948Ssaidi@eecs.umich.edu } else if (sendEvent->when() > when) { 1192948Ssaidi@eecs.umich.edu owner->reschedule(sendEvent, when); 1205529Snate@binkert.org } 1215894Sgblack@eecs.umich.edu} 1225894Sgblack@eecs.umich.edu 1232623SN/Avoid 1242623SN/ASimpleTimingPort::schedSendTiming(PacketPtr pkt, Tick when) 1253647Srdreslin@umich.edu{ 1263647Srdreslin@umich.edu assert(when > curTick()); 1273647Srdreslin@umich.edu assert(when < curTick() + SimClock::Int::ms); 1283647Srdreslin@umich.edu 1292623SN/A // Nothing is on the list: add it and schedule an event 1302839Sktlim@umich.edu if (transmitList.empty() || when < transmitList.front().tick) { 1313222Sktlim@umich.edu transmitList.push_front(DeferredPacket(when, pkt)); 1322901Ssaidi@eecs.umich.edu schedSendEvent(when); 1337897Shestness@cs.utexas.edu return; 1342623SN/A } 1352623SN/A 1362623SN/A // list is non-empty & this belongs at the end 1372623SN/A if (when >= transmitList.back().tick) { 1382623SN/A transmitList.push_back(DeferredPacket(when, pkt)); 1392623SN/A return; 1402623SN/A } 1412623SN/A 1422623SN/A // this belongs in the middle somewhere 1432623SN/A DeferredPacketIterator i = transmitList.begin(); 1442915Sktlim@umich.edu i++; // already checked for insertion at front 1452915Sktlim@umich.edu DeferredPacketIterator end = transmitList.end(); 1462623SN/A 1472623SN/A for (; i != end; ++i) { 1482623SN/A if (when < i->tick) { 1492623SN/A transmitList.insert(i, DeferredPacket(when, pkt)); 1502623SN/A return; 1512623SN/A } 1522915Sktlim@umich.edu } 1532915Sktlim@umich.edu assert(false); // should never get here 1542623SN/A} 1552798Sktlim@umich.edu 1562798Sktlim@umich.edu 1572901Ssaidi@eecs.umich.eduvoid 1582839Sktlim@umich.eduSimpleTimingPort::sendDeferredPacket() 1592798Sktlim@umich.edu{ 1602839Sktlim@umich.edu assert(deferredPacketReady()); 1612798Sktlim@umich.edu // take packet off list here; if recvTiming() on the other side 1625496Ssaidi@eecs.umich.edu // calls sendTiming() back on us (like SimpleTimingCpu does), then 1632901Ssaidi@eecs.umich.edu // we get confused by having a non-active packet on transmitList 1642901Ssaidi@eecs.umich.edu DeferredPacket dp = transmitList.front(); 1652798Sktlim@umich.edu transmitList.pop_front(); 1662839Sktlim@umich.edu bool success = sendTiming(dp.pkt); 1672839Sktlim@umich.edu 1682901Ssaidi@eecs.umich.edu if (success) { 1692798Sktlim@umich.edu if (!transmitList.empty() && !sendEvent->scheduled()) { 1702623SN/A Tick time = transmitList.front().tick; 1712623SN/A owner->schedule(sendEvent, time <= curTick() ? curTick()+1 : time); 1722623SN/A } 1732798Sktlim@umich.edu 1742623SN/A if (transmitList.empty() && drainEvent && !sendEvent->scheduled()) { 1755221Ssaidi@eecs.umich.edu drainEvent->process(); 1762798Sktlim@umich.edu drainEvent = NULL; 1774762Snate@binkert.org } 1783201Shsul@eecs.umich.edu } else { 1795710Scws3k@cs.virginia.edu // Unsuccessful, need to put back on transmitList. Callee 1805710Scws3k@cs.virginia.edu // should not have messed with it (since it didn't accept that 1812915Sktlim@umich.edu // packet), so we can just push it back on the front. 1825710Scws3k@cs.virginia.edu assert(!sendEvent->scheduled()); 1832623SN/A transmitList.push_front(dp); 1842798Sktlim@umich.edu } 1852901Ssaidi@eecs.umich.edu 1862798Sktlim@umich.edu waitingOnRetry = !success; 1872798Sktlim@umich.edu 1882798Sktlim@umich.edu if (waitingOnRetry) { 1892798Sktlim@umich.edu DPRINTF(Bus, "Send failed, waiting on retry\n"); 1902798Sktlim@umich.edu } 1915496Ssaidi@eecs.umich.edu} 1922798Sktlim@umich.edu 1937823Ssteve.reinhardt@amd.com 1942867Sktlim@umich.eduvoid 1952867Sktlim@umich.eduSimpleTimingPort::recvRetry() 1962867Sktlim@umich.edu{ 1975710Scws3k@cs.virginia.edu DPRINTF(Bus, "Received retry\n"); 1985606Snate@binkert.org assert(waitingOnRetry); 1992623SN/A sendDeferredPacket(); 2002623SN/A} 2012623SN/A 2022623SN/A 2032623SN/Avoid 2042623SN/ASimpleTimingPort::processSendEvent() 2054192Sktlim@umich.edu{ 2062623SN/A assert(!waitingOnRetry); 2072680Sktlim@umich.edu sendDeferredPacket(); 2082623SN/A} 2092680Sktlim@umich.edu 2102680Sktlim@umich.edu 2112680Sktlim@umich.eduunsigned int 2122623SN/ASimpleTimingPort::drain(Event *de) 2132623SN/A{ 2142623SN/A if (transmitList.size() == 0 && !sendEvent->scheduled()) 2152623SN/A return 0; 2163201Shsul@eecs.umich.edu drainEvent = de; 2173201Shsul@eecs.umich.edu return 1; 2183201Shsul@eecs.umich.edu} 2193201Shsul@eecs.umich.edu