simple_mem.cc revision 10466:73b7549d979e
1/* 2 * Copyright (c) 2010-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2001-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ron Dreslinski 41 * Ali Saidi 42 * Andreas Hansson 43 */ 44 45#include "base/random.hh" 46#include "mem/simple_mem.hh" 47 48using namespace std; 49 50SimpleMemory::SimpleMemory(const SimpleMemoryParams* p) : 51 AbstractMemory(p), 52 port(name() + ".port", *this), latency(p->latency), 53 latency_var(p->latency_var), bandwidth(p->bandwidth), isBusy(false), 54 retryReq(false), retryResp(false), 55 releaseEvent(this), dequeueEvent(this), drainManager(NULL) 56{ 57} 58 59void 60SimpleMemory::init() 61{ 62 AbstractMemory::init(); 63 64 // allow unconnected memories as this is used in several ruby 65 // systems at the moment 66 if (port.isConnected()) { 67 port.sendRangeChange(); 68 } 69} 70 71Tick 72SimpleMemory::recvAtomic(PacketPtr pkt) 73{ 74 access(pkt); 75 return pkt->memInhibitAsserted() ? 0 : getLatency(); 76} 77 78void 79SimpleMemory::recvFunctional(PacketPtr pkt) 80{ 81 pkt->pushLabel(name()); 82 83 functionalAccess(pkt); 84 85 bool done = false; 86 auto p = packetQueue.begin(); 87 // potentially update the packets in our packet queue as well 88 while (!done && p != packetQueue.end()) { 89 done = pkt->checkFunctional(p->pkt); 90 ++p; 91 } 92 93 pkt->popLabel(); 94} 95 96bool 97SimpleMemory::recvTimingReq(PacketPtr pkt) 98{ 99 /// @todo temporary hack to deal with memory corruption issues until 100 /// 4-phase transactions are complete 101 for (int x = 0; x < pendingDelete.size(); x++) 102 delete pendingDelete[x]; 103 pendingDelete.clear(); 104 105 if (pkt->memInhibitAsserted()) { 106 // snooper will supply based on copy of packet 107 // still target's responsibility to delete packet 108 pendingDelete.push_back(pkt); 109 return true; 110 } 111 112 // we should never get a new request after committing to retry the 113 // current one, the bus violates the rule as it simply sends a 114 // retry to the next one waiting on the retry list, so simply 115 // ignore it 116 if (retryReq) 117 return false; 118 119 // if we are busy with a read or write, remember that we have to 120 // retry 121 if (isBusy) { 122 retryReq = true; 123 return false; 124 } 125 126 // @todo someone should pay for this 127 pkt->firstWordDelay = pkt->lastWordDelay = 0; 128 129 // update the release time according to the bandwidth limit, and 130 // do so with respect to the time it takes to finish this request 131 // rather than long term as it is the short term data rate that is 132 // limited for any real memory 133 134 // only look at reads and writes when determining if we are busy, 135 // and for how long, as it is not clear what to regulate for the 136 // other types of commands 137 if (pkt->isRead() || pkt->isWrite()) { 138 // calculate an appropriate tick to release to not exceed 139 // the bandwidth limit 140 Tick duration = pkt->getSize() * bandwidth; 141 142 // only consider ourselves busy if there is any need to wait 143 // to avoid extra events being scheduled for (infinitely) fast 144 // memories 145 if (duration != 0) { 146 schedule(releaseEvent, curTick() + duration); 147 isBusy = true; 148 } 149 } 150 151 // go ahead and deal with the packet and put the response in the 152 // queue if there is one 153 bool needsResponse = pkt->needsResponse(); 154 recvAtomic(pkt); 155 // turn packet around to go back to requester if response expected 156 if (needsResponse) { 157 // recvAtomic() should already have turned packet into 158 // atomic response 159 assert(pkt->isResponse()); 160 // to keep things simple (and in order), we put the packet at 161 // the end even if the latency suggests it should be sent 162 // before the packet(s) before it 163 packetQueue.push_back(DeferredPacket(pkt, curTick() + getLatency())); 164 if (!retryResp && !dequeueEvent.scheduled()) 165 schedule(dequeueEvent, packetQueue.back().tick); 166 } else { 167 pendingDelete.push_back(pkt); 168 } 169 170 return true; 171} 172 173void 174SimpleMemory::release() 175{ 176 assert(isBusy); 177 isBusy = false; 178 if (retryReq) { 179 retryReq = false; 180 port.sendRetry(); 181 } 182} 183 184void 185SimpleMemory::dequeue() 186{ 187 assert(!packetQueue.empty()); 188 DeferredPacket deferred_pkt = packetQueue.front(); 189 190 retryResp = !port.sendTimingResp(deferred_pkt.pkt); 191 192 if (!retryResp) { 193 packetQueue.pop_front(); 194 195 // if the queue is not empty, schedule the next dequeue event, 196 // otherwise signal that we are drained if we were asked to do so 197 if (!packetQueue.empty()) { 198 // if there were packets that got in-between then we 199 // already have an event scheduled, so use re-schedule 200 reschedule(dequeueEvent, 201 std::max(packetQueue.front().tick, curTick()), true); 202 } else if (drainManager) { 203 drainManager->signalDrainDone(); 204 drainManager = NULL; 205 } 206 } 207} 208 209Tick 210SimpleMemory::getLatency() const 211{ 212 return latency + 213 (latency_var ? random_mt.random<Tick>(0, latency_var) : 0); 214} 215 216void 217SimpleMemory::recvRetry() 218{ 219 assert(retryResp); 220 221 dequeue(); 222} 223 224BaseSlavePort & 225SimpleMemory::getSlavePort(const std::string &if_name, PortID idx) 226{ 227 if (if_name != "port") { 228 return MemObject::getSlavePort(if_name, idx); 229 } else { 230 return port; 231 } 232} 233 234unsigned int 235SimpleMemory::drain(DrainManager *dm) 236{ 237 int count = 0; 238 239 // also track our internal queue 240 if (!packetQueue.empty()) { 241 count += 1; 242 drainManager = dm; 243 } 244 245 if (count) 246 setDrainState(Drainable::Draining); 247 else 248 setDrainState(Drainable::Drained); 249 return count; 250} 251 252SimpleMemory::MemoryPort::MemoryPort(const std::string& _name, 253 SimpleMemory& _memory) 254 : SlavePort(_name, &_memory), memory(_memory) 255{ } 256 257AddrRangeList 258SimpleMemory::MemoryPort::getAddrRanges() const 259{ 260 AddrRangeList ranges; 261 ranges.push_back(memory.getAddrRange()); 262 return ranges; 263} 264 265Tick 266SimpleMemory::MemoryPort::recvAtomic(PacketPtr pkt) 267{ 268 return memory.recvAtomic(pkt); 269} 270 271void 272SimpleMemory::MemoryPort::recvFunctional(PacketPtr pkt) 273{ 274 memory.recvFunctional(pkt); 275} 276 277bool 278SimpleMemory::MemoryPort::recvTimingReq(PacketPtr pkt) 279{ 280 return memory.recvTimingReq(pkt); 281} 282 283void 284SimpleMemory::MemoryPort::recvRetry() 285{ 286 memory.recvRetry(); 287} 288 289SimpleMemory* 290SimpleMemoryParams::create() 291{ 292 return new SimpleMemory(this); 293} 294