se_translating_port_proxy.cc revision 2423
112396SRiken.Gohil@arm.com/* 212811Sandreas.sandberg@arm.com * Copyright (c) 2001-2005 The Regents of The University of Michigan 312396SRiken.Gohil@arm.com * All rights reserved. 412396SRiken.Gohil@arm.com * 512396SRiken.Gohil@arm.com * Redistribution and use in source and binary forms, with or without 612396SRiken.Gohil@arm.com * modification, are permitted provided that the following conditions are 712396SRiken.Gohil@arm.com * met: redistributions of source code must retain the above copyright 812396SRiken.Gohil@arm.com * notice, this list of conditions and the following disclaimer; 912396SRiken.Gohil@arm.com * redistributions in binary form must reproduce the above copyright 1012396SRiken.Gohil@arm.com * notice, this list of conditions and the following disclaimer in the 1112396SRiken.Gohil@arm.com * documentation and/or other materials provided with the distribution; 1212396SRiken.Gohil@arm.com * neither the name of the copyright holders nor the names of its 1312396SRiken.Gohil@arm.com * contributors may be used to endorse or promote products derived from 1412396SRiken.Gohil@arm.com * this software without specific prior written permission. 1512396SRiken.Gohil@arm.com * 1612396SRiken.Gohil@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712396SRiken.Gohil@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812396SRiken.Gohil@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912396SRiken.Gohil@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012396SRiken.Gohil@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112396SRiken.Gohil@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212396SRiken.Gohil@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312396SRiken.Gohil@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412396SRiken.Gohil@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512396SRiken.Gohil@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612396SRiken.Gohil@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712396SRiken.Gohil@arm.com */ 2812396SRiken.Gohil@arm.com 2912396SRiken.Gohil@arm.com#include <string> 3012396SRiken.Gohil@arm.com#include "arch/faults.hh" 3112396SRiken.Gohil@arm.com#include "base/chunk_generator.hh" 3212396SRiken.Gohil@arm.com#include "mem/port.hh" 3312396SRiken.Gohil@arm.com#include "mem/translating_port.hh" 3412396SRiken.Gohil@arm.com#include "mem/page_table.hh" 3512396SRiken.Gohil@arm.com 3612396SRiken.Gohil@arm.comusing namespace TheISA; 3712396SRiken.Gohil@arm.com 3812396SRiken.Gohil@arm.comTranslatingPort::TranslatingPort(Port *_port, PageTable *p_table) 3912396SRiken.Gohil@arm.com : port(_port), pTable(p_table) 4012396SRiken.Gohil@arm.com{ } 4112396SRiken.Gohil@arm.com 4212396SRiken.Gohil@arm.comTranslatingPort::~TranslatingPort() 4312396SRiken.Gohil@arm.com{ } 4412396SRiken.Gohil@arm.com 4512396SRiken.Gohil@arm.comFault 4612396SRiken.Gohil@arm.comTranslatingPort::readBlobFunctional(Addr addr, uint8_t *p, int size) 4712396SRiken.Gohil@arm.com{ 4812396SRiken.Gohil@arm.com Addr paddr; 4912396SRiken.Gohil@arm.com int prevSize = 0; 5012396SRiken.Gohil@arm.com 5112396SRiken.Gohil@arm.com for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) { 5212396SRiken.Gohil@arm.com 5312396SRiken.Gohil@arm.com if (!pTable->translate(gen.addr(),paddr)) 5412396SRiken.Gohil@arm.com return genMachineCheckFault(); 5512396SRiken.Gohil@arm.com 5612396SRiken.Gohil@arm.com port->readBlobFunctional(paddr, p + prevSize, gen.size()); 5712396SRiken.Gohil@arm.com prevSize += gen.size(); 5812396SRiken.Gohil@arm.com } 5912396SRiken.Gohil@arm.com 6012396SRiken.Gohil@arm.com return NoFault; 6112396SRiken.Gohil@arm.com} 6212811Sandreas.sandberg@arm.com 6312396SRiken.Gohil@arm.comFault 6412396SRiken.Gohil@arm.comTranslatingPort::writeBlobFunctional(Addr addr, uint8_t *p, int size, 6512396SRiken.Gohil@arm.com bool alloc) 6612396SRiken.Gohil@arm.com{ 6712396SRiken.Gohil@arm.com Addr paddr; 6812396SRiken.Gohil@arm.com int prevSize = 0; 6912396SRiken.Gohil@arm.com 7012396SRiken.Gohil@arm.com for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) { 7112396SRiken.Gohil@arm.com 7212811Sandreas.sandberg@arm.com if (!pTable->translate(gen.addr(), paddr)) { 7312396SRiken.Gohil@arm.com if (alloc) { 7412396SRiken.Gohil@arm.com pTable->allocate(roundDown(gen.addr(), VMPageSize), 7512396SRiken.Gohil@arm.com VMPageSize); 7612396SRiken.Gohil@arm.com pTable->translate(gen.addr(), paddr); 7712396SRiken.Gohil@arm.com } else { 7812396SRiken.Gohil@arm.com return genMachineCheckFault(); 7912396SRiken.Gohil@arm.com } 8012396SRiken.Gohil@arm.com } 8112396SRiken.Gohil@arm.com 8212844Sgiacomo.travaglini@arm.com port->writeBlobFunctional(paddr, p + prevSize, gen.size()); 8312844Sgiacomo.travaglini@arm.com prevSize += gen.size(); 8412844Sgiacomo.travaglini@arm.com } 8512844Sgiacomo.travaglini@arm.com 8612396SRiken.Gohil@arm.com return NoFault; 8712396SRiken.Gohil@arm.com} 8812844Sgiacomo.travaglini@arm.com 8912844Sgiacomo.travaglini@arm.com 9012844Sgiacomo.travaglini@arm.comFault 9112811Sandreas.sandberg@arm.comTranslatingPort::memsetBlobFunctional(Addr addr, uint8_t val, int size, 9212396SRiken.Gohil@arm.com bool alloc) 9312396SRiken.Gohil@arm.com{ 9412396SRiken.Gohil@arm.com Addr paddr; 9512396SRiken.Gohil@arm.com 9612396SRiken.Gohil@arm.com for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) { 9712396SRiken.Gohil@arm.com 9812396SRiken.Gohil@arm.com if (!pTable->translate(gen.addr(), paddr)) { 9912396SRiken.Gohil@arm.com if (alloc) { 10012396SRiken.Gohil@arm.com pTable->allocate(roundDown(gen.addr(), VMPageSize), 10112396SRiken.Gohil@arm.com VMPageSize); 10212396SRiken.Gohil@arm.com pTable->translate(gen.addr(), paddr); 10312396SRiken.Gohil@arm.com } else { 10412396SRiken.Gohil@arm.com return genMachineCheckFault(); 10512396SRiken.Gohil@arm.com } 10612396SRiken.Gohil@arm.com } 10712396SRiken.Gohil@arm.com 10812396SRiken.Gohil@arm.com port->memsetBlobFunctional(paddr, val, gen.size()); 10912396SRiken.Gohil@arm.com } 110 111 return NoFault; 112} 113 114 115Fault 116TranslatingPort::writeStringFunctional(Addr addr, const char *str) 117{ 118 Addr paddr,vaddr; 119 uint8_t c; 120 121 vaddr = addr; 122 123 do { 124 c = *str++; 125 if (!pTable->translate(vaddr++,paddr)) 126 return genMachineCheckFault(); 127 128 port->writeBlobFunctional(paddr, &c, 1); 129 } while (c); 130 131 return NoFault; 132} 133 134Fault 135TranslatingPort::readStringFunctional(std::string &str, Addr addr) 136{ 137 Addr paddr,vaddr; 138 uint8_t c; 139 140 vaddr = addr; 141 142 do { 143 if (!pTable->translate(vaddr++,paddr)) 144 return genMachineCheckFault(); 145 146 port->readBlobFunctional(paddr, &c, 1); 147 str += c; 148 } while (c); 149 150 return NoFault; 151} 152 153