Sequencer.py revision 8839 
1# Copyright (c) 2009 Advanced Micro Devices, Inc.
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28#          Brad Beckmann
29
30from m5.params import *
31from m5.proxy import *
32from MemObject import MemObject
33
34class RubyPort(MemObject):
35    type = 'RubyPort'
36    abstract = True
37    slave = VectorSlavePort("CPU slave port")
38    master = VectorMasterPort("CPU master port")
39    version = Param.Int(0, "")
40    pio_port = MasterPort("Ruby_pio_port")
41    physmem = Param.PhysicalMemory("")
42    physMemPort = MasterPort("port to physical memory")
43    using_ruby_tester = Param.Bool(False, "")
44    using_network_tester = Param.Bool(False, "")
45    access_phys_mem = Param.Bool(True,
46        "should the rubyport atomically update phys_mem")
47    ruby_system = Param.RubySystem("")
48
49class RubyPortProxy(RubyPort):
50    type = 'RubyPortProxy'
51
52class RubySequencer(RubyPort):
53    type = 'RubySequencer'
54    cxx_class = 'Sequencer'
55    icache = Param.RubyCache("")
56    dcache = Param.RubyCache("")
57    max_outstanding_requests = Param.Int(16,
58        "max requests (incl. prefetches) outstanding")
59    deadlock_threshold = Param.Int(500000,
60        "max outstanding cycles for a request before deadlock/livelock declared")
61
62class DMASequencer(RubyPort):
63    type = 'DMASequencer'
64