Sequencer.py revision 6893
12553SN/Afrom m5.params import * 25254Sksewell@umich.edufrom m5.proxy import * 35254Sksewell@umich.edufrom MemObject import MemObject 42553SN/A 55254Sksewell@umich.educlass RubyPort(MemObject): 65254Sksewell@umich.edu type = 'RubyPort' 75254Sksewell@umich.edu abstract = True 85254Sksewell@umich.edu port = VectorPort("M5 port") 95254Sksewell@umich.edu version = Param.Int(0, "") 105254Sksewell@umich.edu pio_port = Port("Ruby_pio_port") 115254Sksewell@umich.edu physmem = Param.PhysicalMemory("") 125254Sksewell@umich.edu physMemPort = Port("port to physical memory") 135254Sksewell@umich.edu 145254Sksewell@umich.educlass RubySequencer(RubyPort): 152553SN/A type = 'RubySequencer' 165254Sksewell@umich.edu cxx_class = 'Sequencer' 175254Sksewell@umich.edu icache = Param.RubyCache("") 185254Sksewell@umich.edu dcache = Param.RubyCache("") 195254Sksewell@umich.edu max_outstanding_requests = Param.Int(16, 205254Sksewell@umich.edu "max requests (incl. prefetches) outstanding") 215254Sksewell@umich.edu deadlock_threshold = Param.Int(500000, 225254Sksewell@umich.edu "max outstanding cycles for a request before deadlock/livelock declared") 235254Sksewell@umich.edu 245254Sksewell@umich.educlass DMASequencer(RubyPort): 255254Sksewell@umich.edu type = 'DMASequencer' 265254Sksewell@umich.edu