Sequencer.py revision 6882
16876Ssteve.reinhardt@amd.comfrom m5.params import * 26882SBrad.Beckmann@amd.comfrom m5.proxy import * 36876Ssteve.reinhardt@amd.comfrom MemObject import MemObject 46876Ssteve.reinhardt@amd.com 56876Ssteve.reinhardt@amd.comclass RubyPort(MemObject): 66876Ssteve.reinhardt@amd.com type = 'RubyPort' 76876Ssteve.reinhardt@amd.com abstract = True 86876Ssteve.reinhardt@amd.com port = VectorPort("M5 port") 96876Ssteve.reinhardt@amd.com version = Param.Int(0, "") 106882SBrad.Beckmann@amd.com pio_port = Port("Ruby_pio_port") 116876Ssteve.reinhardt@amd.com 126876Ssteve.reinhardt@amd.comclass RubySequencer(RubyPort): 136876Ssteve.reinhardt@amd.com type = 'RubySequencer' 146876Ssteve.reinhardt@amd.com cxx_class = 'Sequencer' 156876Ssteve.reinhardt@amd.com icache = Param.RubyCache("") 166876Ssteve.reinhardt@amd.com dcache = Param.RubyCache("") 176876Ssteve.reinhardt@amd.com max_outstanding_requests = Param.Int(16, 186876Ssteve.reinhardt@amd.com "max requests (incl. prefetches) outstanding") 196876Ssteve.reinhardt@amd.com deadlock_threshold = Param.Int(500000, 206876Ssteve.reinhardt@amd.com "max outstanding cycles for a request before deadlock/livelock declared") 216876Ssteve.reinhardt@amd.com funcmem_port = Port("port to functional memory") 226876Ssteve.reinhardt@amd.com 236876Ssteve.reinhardt@amd.comclass DMASequencer(RubyPort): 246876Ssteve.reinhardt@amd.com type = 'DMASequencer' 25