Sequencer.py revision 6876
16876Ssteve.reinhardt@amd.comfrom m5.params import * 26876Ssteve.reinhardt@amd.comfrom MemObject import MemObject 36876Ssteve.reinhardt@amd.com 46876Ssteve.reinhardt@amd.comclass RubyPort(MemObject): 56876Ssteve.reinhardt@amd.com type = 'RubyPort' 66876Ssteve.reinhardt@amd.com abstract = True 76876Ssteve.reinhardt@amd.com port = VectorPort("M5 port") 86876Ssteve.reinhardt@amd.com controller = Param.RubyController("") 96876Ssteve.reinhardt@amd.com version = Param.Int(0, "") 106876Ssteve.reinhardt@amd.com 116876Ssteve.reinhardt@amd.comclass RubySequencer(RubyPort): 126876Ssteve.reinhardt@amd.com type = 'RubySequencer' 136876Ssteve.reinhardt@amd.com cxx_class = 'Sequencer' 146876Ssteve.reinhardt@amd.com icache = Param.RubyCache("") 156876Ssteve.reinhardt@amd.com dcache = Param.RubyCache("") 166876Ssteve.reinhardt@amd.com max_outstanding_requests = Param.Int(16, 176876Ssteve.reinhardt@amd.com "max requests (incl. prefetches) outstanding") 186876Ssteve.reinhardt@amd.com deadlock_threshold = Param.Int(500000, 196876Ssteve.reinhardt@amd.com "max outstanding cycles for a request before deadlock/livelock declared") 206876Ssteve.reinhardt@amd.com funcmem_port = Port("port to functional memory") 216876Ssteve.reinhardt@amd.com 226876Ssteve.reinhardt@amd.comclass DMASequencer(RubyPort): 236876Ssteve.reinhardt@amd.com type = 'DMASequencer' 24