Sequencer.py revision 13892
12SN/A# Copyright (c) 2009 Advanced Micro Devices, Inc. 21762SN/A# All rights reserved. 32SN/A# 42SN/A# Redistribution and use in source and binary forms, with or without 52SN/A# modification, are permitted provided that the following conditions are 62SN/A# met: redistributions of source code must retain the above copyright 72SN/A# notice, this list of conditions and the following disclaimer; 82SN/A# redistributions in binary form must reproduce the above copyright 92SN/A# notice, this list of conditions and the following disclaimer in the 102SN/A# documentation and/or other materials provided with the distribution; 112SN/A# neither the name of the copyright holders nor the names of its 122SN/A# contributors may be used to endorse or promote products derived from 132SN/A# this software without specific prior written permission. 142SN/A# 152SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262SN/A# 272665Ssaidi@eecs.umich.edu# Authors: Steve Reinhardt 282665Ssaidi@eecs.umich.edu# Brad Beckmann 292SN/A 302SN/Afrom m5.params import * 312SN/Afrom m5.proxy import * 322SN/Afrom m5.objects.ClockedObject import ClockedObject 338229Snate@binkert.org 348229Snate@binkert.orgclass RubyPort(ClockedObject): 352SN/A type = 'RubyPort' 362SN/A abstract = True 378229Snate@binkert.org cxx_header = "mem/ruby/system/RubyPort.hh" 388229Snate@binkert.org version = Param.Int(0, "") 3956SN/A 4056SN/A slave = VectorSlavePort("CPU slave port") 418229Snate@binkert.org master = VectorMasterPort("CPU master port") 422SN/A pio_master_port = MasterPort("Ruby mem master port") 432SN/A mem_master_port = MasterPort("Ruby mem master port") 442SN/A pio_slave_port = SlavePort("Ruby pio slave port") 455523Snate@binkert.org mem_slave_port = SlavePort("Ruby memory port") 465523Snate@binkert.org 475523Snate@binkert.org using_ruby_tester = Param.Bool(False, "") 485523Snate@binkert.org no_retry_on_stall = Param.Bool(False, "") 495523Snate@binkert.org ruby_system = Param.RubySystem(Parent.any, "") 505523Snate@binkert.org system = Param.System(Parent.any, "system object") 515523Snate@binkert.org support_data_reqs = Param.Bool(True, "data cache requests supported") 525523Snate@binkert.org support_inst_reqs = Param.Bool(True, "inst cache requests supported") 535523Snate@binkert.org is_cpu_sequencer = Param.Bool(True, "connected to a cpu") 545523Snate@binkert.org 555523Snate@binkert.orgclass RubyPortProxy(RubyPort): 565523Snate@binkert.org type = 'RubyPortProxy' 575523Snate@binkert.org cxx_header = "mem/ruby/system/RubyPortProxy.hh" 585523Snate@binkert.org 595523Snate@binkert.orgclass RubySequencer(RubyPort): 605523Snate@binkert.org type = 'RubySequencer' 615523Snate@binkert.org cxx_class = 'Sequencer' 622SN/A cxx_header = "mem/ruby/system/Sequencer.hh" 632SN/A 642SN/A icache = Param.RubyCache("") 652SN/A dcache = Param.RubyCache("") 662SN/A # Cache latencies currently assessed at the beginning of each access 672SN/A # NOTE: Setting these values to a value greater than one will result in 682SN/A # O3 CPU pipeline bubbles and negatively impact performance 692SN/A # TODO: Latencies should be migrated into each top-level cache controller 702SN/A icache_hit_latency = Param.Cycles(1, "Inst cache hit latency") 712SN/A dcache_hit_latency = Param.Cycles(1, "Data cache hit latency") 722SN/A max_outstanding_requests = Param.Int(16, 732SN/A "max requests (incl. prefetches) outstanding") 742SN/A deadlock_threshold = Param.Cycles(500000, 752SN/A "max outstanding cycles for a request before deadlock/livelock declared") 762SN/A garnet_standalone = Param.Bool(False, "") 772SN/A # id used by protocols that support multiple sequencers per controller 782SN/A # 99 is the dummy default value 792SN/A coreid = Param.Int(99, "CorePair core id") 802SN/A 812SN/Aclass DMASequencer(RubyPort): 822SN/A type = 'DMASequencer' 832SN/A cxx_header = "mem/ruby/system/DMASequencer.hh" 842SN/A max_outstanding_requests = Param.Int(64, "max outstanding requests") 851290SN/A