Sequencer.py revision 11308
17019SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 27019SBrad.Beckmann@amd.com# All rights reserved. 37019SBrad.Beckmann@amd.com# 47019SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 57019SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 67019SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 77019SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 87019SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 97019SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 107019SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 117019SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 127019SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 137019SBrad.Beckmann@amd.com# this software without specific prior written permission. 147019SBrad.Beckmann@amd.com# 157019SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 167019SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 177019SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 187019SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 197019SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 207019SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 217019SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 227019SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 237019SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 247019SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 257019SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 267019SBrad.Beckmann@amd.com# 277019SBrad.Beckmann@amd.com# Authors: Steve Reinhardt 287019SBrad.Beckmann@amd.com# Brad Beckmann 297019SBrad.Beckmann@amd.com 306876Ssteve.reinhardt@amd.comfrom m5.params import * 316882SBrad.Beckmann@amd.comfrom m5.proxy import * 326876Ssteve.reinhardt@amd.comfrom MemObject import MemObject 336876Ssteve.reinhardt@amd.com 346876Ssteve.reinhardt@amd.comclass RubyPort(MemObject): 3511308Santhony.gutierrez@amd.com type = 'RubyPort' 3611308Santhony.gutierrez@amd.com abstract = True 3711308Santhony.gutierrez@amd.com cxx_header = "mem/ruby/system/RubyPort.hh" 3811308Santhony.gutierrez@amd.com version = Param.Int(0, "") 3910090Snilay@cs.wisc.edu 4011308Santhony.gutierrez@amd.com slave = VectorSlavePort("CPU slave port") 4111308Santhony.gutierrez@amd.com master = VectorMasterPort("CPU master port") 4211308Santhony.gutierrez@amd.com pio_master_port = MasterPort("Ruby mem master port") 4311308Santhony.gutierrez@amd.com mem_master_port = MasterPort("Ruby mem master port") 4411308Santhony.gutierrez@amd.com pio_slave_port = SlavePort("Ruby pio slave port") 4511308Santhony.gutierrez@amd.com mem_slave_port = SlavePort("Ruby memory port") 4610090Snilay@cs.wisc.edu 4711308Santhony.gutierrez@amd.com using_ruby_tester = Param.Bool(False, "") 4811308Santhony.gutierrez@amd.com no_retry_on_stall = Param.Bool(False, "") 4911308Santhony.gutierrez@amd.com ruby_system = Param.RubySystem(Parent.any, "") 5011308Santhony.gutierrez@amd.com system = Param.System(Parent.any, "system object") 5111308Santhony.gutierrez@amd.com support_data_reqs = Param.Bool(True, "data cache requests supported") 5211308Santhony.gutierrez@amd.com support_inst_reqs = Param.Bool(True, "inst cache requests supported") 5311308Santhony.gutierrez@amd.com is_cpu_sequencer = Param.Bool(True, "connected to a cpu") 548932SBrad.Beckmann@amd.com 558706Sandreas.hansson@arm.comclass RubyPortProxy(RubyPort): 5611308Santhony.gutierrez@amd.com type = 'RubyPortProxy' 5711308Santhony.gutierrez@amd.com cxx_header = "mem/ruby/system/RubyPortProxy.hh" 5810919Sbrandon.potter@amd.com 596876Ssteve.reinhardt@amd.comclass RubySequencer(RubyPort): 6011308Santhony.gutierrez@amd.com type = 'RubySequencer' 6111308Santhony.gutierrez@amd.com cxx_class = 'Sequencer' 6211308Santhony.gutierrez@amd.com cxx_header = "mem/ruby/system/Sequencer.hh" 6310090Snilay@cs.wisc.edu 6411308Santhony.gutierrez@amd.com icache = Param.RubyCache("") 6511308Santhony.gutierrez@amd.com dcache = Param.RubyCache("") 6611308Santhony.gutierrez@amd.com # Cache latencies currently assessed at the beginning of each access 6711308Santhony.gutierrez@amd.com # NOTE: Setting these values to a value greater than one will result in 6811308Santhony.gutierrez@amd.com # O3 CPU pipeline bubbles and negatively impact performance 6911308Santhony.gutierrez@amd.com # TODO: Latencies should be migrated into each top-level cache controller 7011308Santhony.gutierrez@amd.com icache_hit_latency = Param.Cycles(1, "Inst cache hit latency") 7111308Santhony.gutierrez@amd.com dcache_hit_latency = Param.Cycles(1, "Data cache hit latency") 7211308Santhony.gutierrez@amd.com max_outstanding_requests = Param.Int(16, 7311308Santhony.gutierrez@amd.com "max requests (incl. prefetches) outstanding") 7411308Santhony.gutierrez@amd.com deadlock_threshold = Param.Cycles(500000, 7511308Santhony.gutierrez@amd.com "max outstanding cycles for a request before deadlock/livelock declared") 7611308Santhony.gutierrez@amd.com using_network_tester = Param.Bool(False, "") 7711308Santhony.gutierrez@amd.com # id used by protocols that support multiple sequencers per controller 7811308Santhony.gutierrez@amd.com # 99 is the dummy default value 7911308Santhony.gutierrez@amd.com coreid = Param.Int(99, "CorePair core id") 806876Ssteve.reinhardt@amd.com 8110518Snilay@cs.wisc.educlass DMASequencer(MemObject): 8211308Santhony.gutierrez@amd.com type = 'DMASequencer' 8311308Santhony.gutierrez@amd.com cxx_header = "mem/ruby/system/DMASequencer.hh" 8410519Snilay@cs.wisc.edu 8511308Santhony.gutierrez@amd.com version = Param.Int(0, "") 8611308Santhony.gutierrez@amd.com slave = SlavePort("Device slave port") 8711308Santhony.gutierrez@amd.com using_ruby_tester = Param.Bool(False, "") 8811308Santhony.gutierrez@amd.com ruby_system = Param.RubySystem(Parent.any, "") 8911308Santhony.gutierrez@amd.com system = Param.System(Parent.any, "system object") 90