Sequencer.py revision 10519
17019SBrad.Beckmann@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc. 27019SBrad.Beckmann@amd.com# All rights reserved. 37019SBrad.Beckmann@amd.com# 47019SBrad.Beckmann@amd.com# Redistribution and use in source and binary forms, with or without 57019SBrad.Beckmann@amd.com# modification, are permitted provided that the following conditions are 67019SBrad.Beckmann@amd.com# met: redistributions of source code must retain the above copyright 77019SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer; 87019SBrad.Beckmann@amd.com# redistributions in binary form must reproduce the above copyright 97019SBrad.Beckmann@amd.com# notice, this list of conditions and the following disclaimer in the 107019SBrad.Beckmann@amd.com# documentation and/or other materials provided with the distribution; 117019SBrad.Beckmann@amd.com# neither the name of the copyright holders nor the names of its 127019SBrad.Beckmann@amd.com# contributors may be used to endorse or promote products derived from 137019SBrad.Beckmann@amd.com# this software without specific prior written permission. 147019SBrad.Beckmann@amd.com# 157019SBrad.Beckmann@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 167019SBrad.Beckmann@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 177019SBrad.Beckmann@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 187019SBrad.Beckmann@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 197019SBrad.Beckmann@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 207019SBrad.Beckmann@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 217019SBrad.Beckmann@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 227019SBrad.Beckmann@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 237019SBrad.Beckmann@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 247019SBrad.Beckmann@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 257019SBrad.Beckmann@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 267019SBrad.Beckmann@amd.com# 277019SBrad.Beckmann@amd.com# Authors: Steve Reinhardt 287019SBrad.Beckmann@amd.com# Brad Beckmann 297019SBrad.Beckmann@amd.com 306876Ssteve.reinhardt@amd.comfrom m5.params import * 316882SBrad.Beckmann@amd.comfrom m5.proxy import * 326876Ssteve.reinhardt@amd.comfrom MemObject import MemObject 336876Ssteve.reinhardt@amd.com 346876Ssteve.reinhardt@amd.comclass RubyPort(MemObject): 356876Ssteve.reinhardt@amd.com type = 'RubyPort' 366876Ssteve.reinhardt@amd.com abstract = True 379338SAndreas.Sandberg@arm.com cxx_header = "mem/ruby/system/RubyPort.hh" 3810090Snilay@cs.wisc.edu version = Param.Int(0, "") 3910090Snilay@cs.wisc.edu 408839Sandreas.hansson@arm.com slave = VectorSlavePort("CPU slave port") 418839Sandreas.hansson@arm.com master = VectorMasterPort("CPU master port") 4210090Snilay@cs.wisc.edu pio_master_port = MasterPort("Ruby mem master port") 4310090Snilay@cs.wisc.edu mem_master_port = MasterPort("Ruby mem master port") 4410090Snilay@cs.wisc.edu pio_slave_port = SlavePort("Ruby pio slave port") 4510090Snilay@cs.wisc.edu mem_slave_port = SlavePort("Ruby memory port") 4610090Snilay@cs.wisc.edu 477910SBrad.Beckmann@amd.com using_ruby_tester = Param.Bool(False, "") 489577Snilay@cs.wisc.edu access_phys_mem = Param.Bool(False, 497915SBrad.Beckmann@amd.com "should the rubyport atomically update phys_mem") 508436SBrad.Beckmann@amd.com ruby_system = Param.RubySystem("") 518923Sandreas.hansson@arm.com system = Param.System(Parent.any, "system object") 528932SBrad.Beckmann@amd.com support_data_reqs = Param.Bool(True, "data cache requests supported") 538932SBrad.Beckmann@amd.com support_inst_reqs = Param.Bool(True, "inst cache requests supported") 548932SBrad.Beckmann@amd.com 558706Sandreas.hansson@arm.comclass RubyPortProxy(RubyPort): 568706Sandreas.hansson@arm.com type = 'RubyPortProxy' 579338SAndreas.Sandberg@arm.com cxx_header = "mem/ruby/system/RubyPortProxy.hh" 589577Snilay@cs.wisc.edu access_phys_mem = True 597915SBrad.Beckmann@amd.com 606876Ssteve.reinhardt@amd.comclass RubySequencer(RubyPort): 616876Ssteve.reinhardt@amd.com type = 'RubySequencer' 626876Ssteve.reinhardt@amd.com cxx_class = 'Sequencer' 639338SAndreas.Sandberg@arm.com cxx_header = "mem/ruby/system/Sequencer.hh" 6410090Snilay@cs.wisc.edu 656876Ssteve.reinhardt@amd.com icache = Param.RubyCache("") 666876Ssteve.reinhardt@amd.com dcache = Param.RubyCache("") 676876Ssteve.reinhardt@amd.com max_outstanding_requests = Param.Int(16, 686876Ssteve.reinhardt@amd.com "max requests (incl. prefetches) outstanding") 699184Sandreas.hansson@arm.com deadlock_threshold = Param.Cycles(500000, 706876Ssteve.reinhardt@amd.com "max outstanding cycles for a request before deadlock/livelock declared") 7110090Snilay@cs.wisc.edu using_network_tester = Param.Bool(False, "") 726876Ssteve.reinhardt@amd.com 7310518Snilay@cs.wisc.educlass DMASequencer(MemObject): 746876Ssteve.reinhardt@amd.com type = 'DMASequencer' 759338SAndreas.Sandberg@arm.com cxx_header = "mem/ruby/system/DMASequencer.hh" 7610519Snilay@cs.wisc.edu 7710518Snilay@cs.wisc.edu version = Param.Int(0, "") 7810518Snilay@cs.wisc.edu slave = SlavePort("Device slave port") 7910518Snilay@cs.wisc.edu using_ruby_tester = Param.Bool(False, "") 8010518Snilay@cs.wisc.edu ruby_system = Param.RubySystem(Parent.any, "") 8110518Snilay@cs.wisc.edu system = Param.System(Parent.any, "system object") 82