Sequencer.hh revision 9773:915be89faf30
1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __MEM_RUBY_SYSTEM_SEQUENCER_HH__ 30#define __MEM_RUBY_SYSTEM_SEQUENCER_HH__ 31 32#include <iostream> 33 34#include "base/hashmap.hh" 35#include "mem/protocol/MachineType.hh" 36#include "mem/protocol/RubyRequestType.hh" 37#include "mem/protocol/SequencerRequestType.hh" 38#include "mem/ruby/common/Address.hh" 39#include "mem/ruby/system/CacheMemory.hh" 40#include "mem/ruby/system/RubyPort.hh" 41#include "params/RubySequencer.hh" 42 43class DataBlock; 44 45struct SequencerRequest 46{ 47 PacketPtr pkt; 48 RubyRequestType m_type; 49 Cycles issue_time; 50 51 SequencerRequest(PacketPtr _pkt, RubyRequestType _m_type, 52 Cycles _issue_time) 53 : pkt(_pkt), m_type(_m_type), issue_time(_issue_time) 54 {} 55}; 56 57std::ostream& operator<<(std::ostream& out, const SequencerRequest& obj); 58 59class Sequencer : public RubyPort 60{ 61 public: 62 typedef RubySequencerParams Params; 63 Sequencer(const Params *); 64 ~Sequencer(); 65 66 // Public Methods 67 void wakeup(); // Used only for deadlock detection 68 void printProgress(std::ostream& out) const; 69 void clearStats(); 70 71 void writeCallback(const Address& address, 72 DataBlock& data, 73 const bool externalHit = false, 74 const MachineType mach = MachineType_NUM, 75 const Cycles initialRequestTime = Cycles(0), 76 const Cycles forwardRequestTime = Cycles(0), 77 const Cycles firstResponseTime = Cycles(0)); 78 79 void readCallback(const Address& address, 80 DataBlock& data, 81 const bool externalHit = false, 82 const MachineType mach = MachineType_NUM, 83 const Cycles initialRequestTime = Cycles(0), 84 const Cycles forwardRequestTime = Cycles(0), 85 const Cycles firstResponseTime = Cycles(0)); 86 87 RequestStatus makeRequest(PacketPtr pkt); 88 bool empty() const; 89 int outstandingCount() const { return m_outstanding_count; } 90 91 bool isDeadlockEventScheduled() const 92 { return deadlockCheckEvent.scheduled(); } 93 94 void descheduleDeadlockEvent() 95 { deschedule(deadlockCheckEvent); } 96 97 void print(std::ostream& out) const; 98 void printStats(std::ostream& out) const; 99 void checkCoherence(const Address& address); 100 101 void markRemoved(); 102 void removeRequest(SequencerRequest* request); 103 void evictionCallback(const Address& address); 104 void invalidateSC(const Address& address); 105 106 void recordRequestType(SequencerRequestType requestType); 107 Histogram& getOutstandReqHist() { return m_outstandReqHist; } 108 109 Histogram& getLatencyHist() { return m_latencyHist; } 110 Histogram& getTypeLatencyHist(uint32_t t) 111 { return m_typeLatencyHist[t]; } 112 113 Histogram& getHitLatencyHist() { return m_hitLatencyHist; } 114 Histogram& getHitTypeLatencyHist(uint32_t t) 115 { return m_hitTypeLatencyHist[t]; } 116 117 Histogram& getHitMachLatencyHist(uint32_t t) 118 { return m_hitMachLatencyHist[t]; } 119 120 Histogram& getHitTypeMachLatencyHist(uint32_t r, uint32_t t) 121 { return m_hitTypeMachLatencyHist[r][t]; } 122 123 Histogram& getMissLatencyHist() { return m_missLatencyHist; } 124 Histogram& getMissTypeLatencyHist(uint32_t t) 125 { return m_missTypeLatencyHist[t]; } 126 127 Histogram& getMissMachLatencyHist(uint32_t t) 128 { return m_missMachLatencyHist[t]; } 129 130 Histogram& getMissTypeMachLatencyHist(uint32_t r, uint32_t t) 131 { return m_missTypeMachLatencyHist[r][t]; } 132 133 Histogram& getIssueToInitialDelayHist(uint32_t t) 134 { return m_IssueToInitialDelayHist[t]; } 135 136 Histogram& getInitialToForwardDelayHist(const MachineType t) 137 { return m_InitialToForwardDelayHist[t]; } 138 139 Histogram& getForwardRequestToFirstResponseHist(const MachineType t) 140 { return m_ForwardToFirstResponseDelayHist[t]; } 141 142 Histogram& getFirstResponseToCompletionDelayHist(const MachineType t) 143 { return m_FirstResponseToCompletionDelayHist[t]; } 144 145 const uint64_t getIncompleteTimes(const MachineType t) const 146 { return m_IncompleteTimes[t]; } 147 148 private: 149 void issueRequest(PacketPtr pkt, RubyRequestType type); 150 151 void hitCallback(SequencerRequest* request, DataBlock& data, 152 bool llscSuccess, 153 const MachineType mach, const bool externalHit, 154 const Cycles initialRequestTime, 155 const Cycles forwardRequestTime, 156 const Cycles firstResponseTime); 157 158 void recordMissLatency(const Cycles t, const RubyRequestType type, 159 const MachineType respondingMach, 160 bool isExternalHit, Cycles issuedTime, 161 Cycles initialRequestTime, 162 Cycles forwardRequestTime, Cycles firstResponseTime, 163 Cycles completionTime); 164 165 RequestStatus insertRequest(PacketPtr pkt, RubyRequestType request_type); 166 bool handleLlsc(const Address& address, SequencerRequest* request); 167 168 // Private copy constructor and assignment operator 169 Sequencer(const Sequencer& obj); 170 Sequencer& operator=(const Sequencer& obj); 171 172 private: 173 int m_max_outstanding_requests; 174 Cycles m_deadlock_threshold; 175 176 CacheMemory* m_dataCache_ptr; 177 CacheMemory* m_instCache_ptr; 178 179 typedef m5::hash_map<Address, SequencerRequest*> RequestTable; 180 RequestTable m_writeRequestTable; 181 RequestTable m_readRequestTable; 182 // Global outstanding request count, across all request tables 183 int m_outstanding_count; 184 bool m_deadlock_check_scheduled; 185 186 uint32_t m_store_waiting_on_load_cycles; 187 uint32_t m_store_waiting_on_store_cycles; 188 uint32_t m_load_waiting_on_store_cycles; 189 uint32_t m_load_waiting_on_load_cycles; 190 191 bool m_usingNetworkTester; 192 193 //! Histogram for number of outstanding requests per cycle. 194 Histogram m_outstandReqHist; 195 196 //! Histogram for holding latency profile of all requests. 197 Histogram m_latencyHist; 198 std::vector<Histogram> m_typeLatencyHist; 199 200 //! Histogram for holding latency profile of all requests that 201 //! hit in the controller connected to this sequencer. 202 Histogram m_hitLatencyHist; 203 std::vector<Histogram> m_hitTypeLatencyHist; 204 205 //! Histograms for profiling the latencies for requests that 206 //! did not required external messages. 207 std::vector<Histogram> m_hitMachLatencyHist; 208 std::vector< std::vector<Histogram> > m_hitTypeMachLatencyHist; 209 210 //! Histogram for holding latency profile of all requests that 211 //! miss in the controller connected to this sequencer. 212 Histogram m_missLatencyHist; 213 std::vector<Histogram> m_missTypeLatencyHist; 214 215 //! Histograms for profiling the latencies for requests that 216 //! required external messages. 217 std::vector<Histogram> m_missMachLatencyHist; 218 std::vector< std::vector<Histogram> > m_missTypeMachLatencyHist; 219 220 //! Histograms for recording the breakdown of miss latency 221 std::vector<Histogram> m_IssueToInitialDelayHist; 222 std::vector<Histogram> m_InitialToForwardDelayHist; 223 std::vector<Histogram> m_ForwardToFirstResponseDelayHist; 224 std::vector<Histogram> m_FirstResponseToCompletionDelayHist; 225 std::vector<uint64_t> m_IncompleteTimes; 226 227 228 class SequencerWakeupEvent : public Event 229 { 230 private: 231 Sequencer *m_sequencer_ptr; 232 233 public: 234 SequencerWakeupEvent(Sequencer *_seq) : m_sequencer_ptr(_seq) {} 235 void process() { m_sequencer_ptr->wakeup(); } 236 const char *description() const { return "Sequencer deadlock check"; } 237 }; 238 239 SequencerWakeupEvent deadlockCheckEvent; 240}; 241 242inline std::ostream& 243operator<<(std::ostream& out, const Sequencer& obj) 244{ 245 obj.print(out); 246 out << std::flush; 247 return out; 248} 249 250#endif // __MEM_RUBY_SYSTEM_SEQUENCER_HH__ 251