Sequencer.hh revision 6285:ce086eca1ede 
1
2/*
3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/*
31 * $Id: Sequencer.hh 1.70 2006/09/27 14:56:41-05:00 bobba@s1-01.cs.wisc.edu $
32 *
33 * Description:
34 *
35 */
36
37#ifndef SEQUENCER_H
38#define SEQUENCER_H
39
40#include "mem/ruby/common/Global.hh"
41#include "mem/ruby/config/RubyConfig.hh"
42#include "mem/ruby/common/Consumer.hh"
43#include "mem/protocol/CacheRequestType.hh"
44#include "mem/protocol/AccessModeType.hh"
45#include "mem/protocol/GenericMachineType.hh"
46#include "mem/protocol/PrefetchBit.hh"
47#include "mem/ruby/system/RubyPort.hh"
48#include "mem/gems_common/Map.hh"
49#include "mem/ruby/common/Address.hh"
50
51class DataBlock;
52class CacheMsg;
53class MachineID;
54class CacheMemory;
55class AbstractController;
56
57struct SequencerRequest {
58  RubyRequest ruby_request;
59  int64_t id;
60  Time issue_time;
61
62  SequencerRequest(const RubyRequest & _ruby_request, int64_t _id, Time _issue_time)
63    : ruby_request(_ruby_request), id(_id), issue_time(_issue_time)
64  {}
65};
66
67class Sequencer : public Consumer, public RubyPort {
68public:
69  // Constructors
70  Sequencer(const string & name);
71  void init(const vector<string> & argv);
72
73  // Destructor
74  ~Sequencer();
75
76  // Public Methods
77  void wakeup(); // Used only for deadlock detection
78
79  void printConfig(ostream& out) const;
80
81  void printProgress(ostream& out) const;
82
83  void writeCallback(const Address& address, DataBlock& data);
84  void readCallback(const Address& address, DataBlock& data);
85
86  // called by Tester or Simics
87  int64_t makeRequest(const RubyRequest & request);
88  bool isReady(const RubyRequest& request) const;
89  bool empty() const;
90
91  void print(ostream& out) const;
92  void checkCoherence(const Address& address);
93
94  //  bool getRubyMemoryValue(const Address& addr, char* value, unsigned int size_in_bytes);
95  //  bool setRubyMemoryValue(const Address& addr, char *value, unsigned int size_in_bytes);
96
97  void removeRequest(SequencerRequest* request);
98private:
99  // Private Methods
100  bool tryCacheAccess(const Address& addr, CacheRequestType type, const Address& pc, AccessModeType access_mode, int size, DataBlock*& data_ptr);
101  void issueRequest(const RubyRequest& request);
102
103  void hitCallback(SequencerRequest* request, DataBlock& data);
104  bool insertRequest(SequencerRequest* request);
105
106
107  // Private copy constructor and assignment operator
108  Sequencer(const Sequencer& obj);
109  Sequencer& operator=(const Sequencer& obj);
110
111private:
112  int m_max_outstanding_requests;
113  int m_deadlock_threshold;
114
115  AbstractController* m_controller;
116  MessageBuffer* m_mandatory_q_ptr;
117  CacheMemory* m_dataCache_ptr;
118  CacheMemory* m_instCache_ptr;
119
120  // indicates what processor on the chip this sequencer is associated with
121  int m_version;
122  int m_controller_type;
123
124  Map<Address, SequencerRequest*> m_writeRequestTable;
125  Map<Address, SequencerRequest*> m_readRequestTable;
126  // Global outstanding request count, across all request tables
127  int m_outstanding_count;
128  bool m_deadlock_check_scheduled;
129
130};
131
132// Output operator declaration
133ostream& operator<<(ostream& out, const Sequencer& obj);
134
135// ******************* Definitions *******************
136
137// Output operator definition
138extern inline
139ostream& operator<<(ostream& out, const Sequencer& obj)
140{
141  obj.print(out);
142  out << flush;
143  return out;
144}
145
146#endif //SEQUENCER_H
147
148