Sequencer.hh revision 6152:705b277e1141 
1
2/*
3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/*
31 * $Id: Sequencer.h 1.70 2006/09/27 14:56:41-05:00 bobba@s1-01.cs.wisc.edu $
32 *
33 * Description:
34 *
35 */
36
37#ifndef SEQUENCER_H
38#define SEQUENCER_H
39
40#include "Global.hh"
41#include "RubyConfig.hh"
42#include "Consumer.hh"
43#include "CacheRequestType.hh"
44#include "AccessModeType.hh"
45#include "GenericMachineType.hh"
46#include "PrefetchBit.hh"
47#include "Map.hh"
48#include "packet.hh"
49
50class DataBlock;
51class AbstractChip;
52class CacheMsg;
53class Address;
54class MachineID;
55
56class Sequencer : public Consumer {
57public:
58  // Constructors
59  Sequencer(AbstractChip* chip_ptr, int version);
60
61  // Destructor
62  ~Sequencer();
63
64  // Public Methods
65  void wakeup(); // Used only for deadlock detection
66
67  static void printConfig(ostream& out);
68
69  // returns total number of outstanding request (includes prefetches)
70  int getNumberOutstanding();
71  // return only total number of outstanding demand requests
72  int getNumberOutstandingDemand();
73  // return only total number of outstanding prefetch requests
74  int getNumberOutstandingPrefetch();
75
76  // remove load/store request from queue
77  void removeLoadRequest(const Address & addr, int thread);
78  void removeStoreRequest(const Address & addr, int thread);
79
80  void printProgress(ostream& out) const;
81
82  // returns a pointer to the request in the request tables
83  CacheMsg & getReadRequest( const Address & addr, int thread );
84  CacheMsg & getWriteRequest( const Address & addr, int thread );
85
86  void writeCallback(const Address& address, DataBlock& data);
87  void readCallback(const Address& address, DataBlock& data);
88  void writeCallback(const Address& address);
89  void readCallback(const Address& address);
90  void writeCallback(const Address& address, DataBlock& data, GenericMachineType respondingMach, PrefetchBit pf, int thread);
91  void readCallback(const Address& address, DataBlock& data, GenericMachineType respondingMach, PrefetchBit pf, int thread);
92  void writeCallback(const Address& address, DataBlock& data, GenericMachineType respondingMach, int thread);
93  void readCallback(const Address& address, DataBlock& data, GenericMachineType respondingMach, int thread);
94
95  // returns the thread ID of the request
96  int getRequestThreadID(const Address & addr);
97  // returns the physical address of the request
98  Address getRequestPhysicalAddress(const Address & lineaddr);
99  // returns whether a request is a prefetch request
100  bool isPrefetchRequest(const Address & lineaddr);
101
102  //notifies driver of debug print
103  void printDebug();
104
105  // called by Tester or Simics
106  void makeRequest(const Packet* pkt, void* data);
107  void makeRequest(const CacheMsg& request); // depricate this function
108  bool doRequest(const CacheMsg& request);
109  void issueRequest(const CacheMsg& request);
110  bool isReady(const Packet* pkt) const;
111  bool isReady(const CacheMsg& request) const; // depricate this function
112  bool empty() const;
113  void resetRequestTime(const Address& addr, int thread);
114  Address getLogicalAddressOfRequest(Address address, int thread);
115  AccessModeType getAccessModeOfRequest(Address address, int thread);
116  //uint64 getSequenceNumberOfRequest(Address addr, int thread);
117
118  void print(ostream& out) const;
119  void checkCoherence(const Address& address);
120
121  bool getRubyMemoryValue(const Address& addr, char* value, unsigned int size_in_bytes);
122  bool setRubyMemoryValue(const Address& addr, char *value, unsigned int size_in_bytes);
123
124  void removeRequest(const CacheMsg& request);
125private:
126  // Private Methods
127  bool tryCacheAccess(const Address& addr, CacheRequestType type, const Address& pc, AccessModeType access_mode, int size, DataBlock*& data_ptr);
128  //  void conflictCallback(const CacheMsg& request, GenericMachineType respondingMach, int thread);
129  void hitCallback(const CacheMsg& request, DataBlock& data, GenericMachineType respondingMach, int thread);
130  bool insertRequest(const CacheMsg& request);
131
132
133  // Private copy constructor and assignment operator
134  Sequencer(const Sequencer& obj);
135  Sequencer& operator=(const Sequencer& obj);
136
137  // Data Members (m_ prefix)
138  AbstractChip* m_chip_ptr;
139
140  // indicates what processor on the chip this sequencer is associated with
141  int m_version;
142
143  // One request table per SMT thread
144  Map<Address, CacheMsg>** m_writeRequestTable_ptr;
145  Map<Address, CacheMsg>** m_readRequestTable_ptr;
146  // Global outstanding request count, across all request tables
147  int m_outstanding_count;
148  bool m_deadlock_check_scheduled;
149
150};
151
152// Output operator declaration
153ostream& operator<<(ostream& out, const Sequencer& obj);
154
155// ******************* Definitions *******************
156
157// Output operator definition
158extern inline
159ostream& operator<<(ostream& out, const Sequencer& obj)
160{
161  obj.print(out);
162  out << flush;
163  return out;
164}
165
166#endif //SEQUENCER_H
167
168