Sequencer.hh revision 6145
1 2/* 3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30/* 31 * $Id: Sequencer.h 1.70 2006/09/27 14:56:41-05:00 bobba@s1-01.cs.wisc.edu $ 32 * 33 * Description: 34 * 35 */ 36 37#ifndef SEQUENCER_H 38#define SEQUENCER_H 39 40#include "Global.hh" 41#include "RubyConfig.hh" 42#include "Consumer.hh" 43#include "CacheRequestType.hh" 44#include "AccessModeType.hh" 45#include "GenericMachineType.hh" 46#include "PrefetchBit.hh" 47#include "Map.hh" 48 49class DataBlock; 50class AbstractChip; 51class CacheMsg; 52class Address; 53class MachineID; 54 55class Sequencer : public Consumer { 56public: 57 // Constructors 58 Sequencer(AbstractChip* chip_ptr, int version); 59 60 // Destructor 61 ~Sequencer(); 62 63 // Public Methods 64 void wakeup(); // Used only for deadlock detection 65 66 static void printConfig(ostream& out); 67 68 // returns total number of outstanding request (includes prefetches) 69 int getNumberOutstanding(); 70 // return only total number of outstanding demand requests 71 int getNumberOutstandingDemand(); 72 // return only total number of outstanding prefetch requests 73 int getNumberOutstandingPrefetch(); 74 75 // remove load/store request from queue 76 void removeLoadRequest(const Address & addr, int thread); 77 void removeStoreRequest(const Address & addr, int thread); 78 79 void printProgress(ostream& out) const; 80 81 // returns a pointer to the request in the request tables 82 CacheMsg & getReadRequest( const Address & addr, int thread ); 83 CacheMsg & getWriteRequest( const Address & addr, int thread ); 84 85 // called by Ruby when transaction completes 86 void writeConflictCallback(const Address& address); 87 void readConflictCallback(const Address& address); 88 void writeConflictCallback(const Address& address, GenericMachineType respondingMach, int thread); 89 void readConflictCallback(const Address& address, GenericMachineType respondingMach, int thread); 90 91 void writeCallback(const Address& address, DataBlock& data); 92 void readCallback(const Address& address, DataBlock& data); 93 void writeCallback(const Address& address); 94 void readCallback(const Address& address); 95 void writeCallback(const Address& address, DataBlock& data, GenericMachineType respondingMach, PrefetchBit pf, int thread); 96 void readCallback(const Address& address, DataBlock& data, GenericMachineType respondingMach, PrefetchBit pf, int thread); 97 void writeCallback(const Address& address, DataBlock& data, GenericMachineType respondingMach, int thread); 98 void readCallback(const Address& address, DataBlock& data, GenericMachineType respondingMach, int thread); 99 100 // returns the thread ID of the request 101 int getRequestThreadID(const Address & addr); 102 // returns the physical address of the request 103 Address getRequestPhysicalAddress(const Address & lineaddr); 104 // returns whether a request is a prefetch request 105 bool isPrefetchRequest(const Address & lineaddr); 106 107 //notifies driver of debug print 108 void printDebug(); 109 110 // called by Tester or Simics 111 void makeRequest(const CacheMsg& request); 112 bool doRequest(const CacheMsg& request); 113 void issueRequest(const CacheMsg& request); 114 bool isReady(const CacheMsg& request) const; 115 bool empty() const; 116 void resetRequestTime(const Address& addr, int thread); 117 Address getLogicalAddressOfRequest(Address address, int thread); 118 AccessModeType getAccessModeOfRequest(Address address, int thread); 119 //uint64 getSequenceNumberOfRequest(Address addr, int thread); 120 121 void print(ostream& out) const; 122 void checkCoherence(const Address& address); 123 124 bool getRubyMemoryValue(const Address& addr, char* value, unsigned int size_in_bytes); 125 bool setRubyMemoryValue(const Address& addr, char *value, unsigned int size_in_bytes); 126 127 void removeRequest(const CacheMsg& request); 128private: 129 // Private Methods 130 bool tryCacheAccess(const Address& addr, CacheRequestType type, const Address& pc, AccessModeType access_mode, int size, DataBlock*& data_ptr); 131 void conflictCallback(const CacheMsg& request, GenericMachineType respondingMach, int thread); 132 void hitCallback(const CacheMsg& request, DataBlock& data, GenericMachineType respondingMach, int thread); 133 bool insertRequest(const CacheMsg& request); 134 135 136 // Private copy constructor and assignment operator 137 Sequencer(const Sequencer& obj); 138 Sequencer& operator=(const Sequencer& obj); 139 140 // Data Members (m_ prefix) 141 AbstractChip* m_chip_ptr; 142 143 // indicates what processor on the chip this sequencer is associated with 144 int m_version; 145 146 // One request table per SMT thread 147 Map<Address, CacheMsg>** m_writeRequestTable_ptr; 148 Map<Address, CacheMsg>** m_readRequestTable_ptr; 149 // Global outstanding request count, across all request tables 150 int m_outstanding_count; 151 bool m_deadlock_check_scheduled; 152 153}; 154 155// Output operator declaration 156ostream& operator<<(ostream& out, const Sequencer& obj); 157 158// ******************* Definitions ******************* 159 160// Output operator definition 161extern inline 162ostream& operator<<(ostream& out, const Sequencer& obj) 163{ 164 obj.print(out); 165 out << flush; 166 return out; 167} 168 169#endif //SEQUENCER_H 170 171