Sequencer.hh revision 11168:f98eb2da15a4 
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __MEM_RUBY_SYSTEM_SEQUENCER_HH__
30#define __MEM_RUBY_SYSTEM_SEQUENCER_HH__
31
32#include <iostream>
33#include <unordered_map>
34
35#include "mem/protocol/MachineType.hh"
36#include "mem/protocol/RubyRequestType.hh"
37#include "mem/protocol/SequencerRequestType.hh"
38#include "mem/ruby/common/Address.hh"
39#include "mem/ruby/structures/CacheMemory.hh"
40#include "mem/ruby/system/RubyPort.hh"
41#include "params/RubySequencer.hh"
42
43struct SequencerRequest
44{
45    PacketPtr pkt;
46    RubyRequestType m_type;
47    Cycles issue_time;
48
49    SequencerRequest(PacketPtr _pkt, RubyRequestType _m_type,
50                     Cycles _issue_time)
51        : pkt(_pkt), m_type(_m_type), issue_time(_issue_time)
52    {}
53};
54
55std::ostream& operator<<(std::ostream& out, const SequencerRequest& obj);
56
57class Sequencer : public RubyPort
58{
59  public:
60    typedef RubySequencerParams Params;
61    Sequencer(const Params *);
62    ~Sequencer();
63
64    // Public Methods
65    void wakeup(); // Used only for deadlock detection
66    void resetStats();
67    void collateStats();
68    void regStats();
69
70    void writeCallback(Addr address,
71                       DataBlock& data,
72                       const bool externalHit = false,
73                       const MachineType mach = MachineType_NUM,
74                       const Cycles initialRequestTime = Cycles(0),
75                       const Cycles forwardRequestTime = Cycles(0),
76                       const Cycles firstResponseTime = Cycles(0));
77
78    void readCallback(Addr address,
79                      DataBlock& data,
80                      const bool externalHit = false,
81                      const MachineType mach = MachineType_NUM,
82                      const Cycles initialRequestTime = Cycles(0),
83                      const Cycles forwardRequestTime = Cycles(0),
84                      const Cycles firstResponseTime = Cycles(0));
85
86    RequestStatus makeRequest(PacketPtr pkt);
87    bool empty() const;
88    int outstandingCount() const { return m_outstanding_count; }
89
90    bool isDeadlockEventScheduled() const
91    { return deadlockCheckEvent.scheduled(); }
92
93    void descheduleDeadlockEvent()
94    { deschedule(deadlockCheckEvent); }
95
96    void print(std::ostream& out) const;
97    void checkCoherence(Addr address);
98
99    void markRemoved();
100    void evictionCallback(Addr address);
101    void invalidateSC(Addr address);
102
103    void recordRequestType(SequencerRequestType requestType);
104    Stats::Histogram& getOutstandReqHist() { return m_outstandReqHist; }
105
106    Stats::Histogram& getLatencyHist() { return m_latencyHist; }
107    Stats::Histogram& getTypeLatencyHist(uint32_t t)
108    { return *m_typeLatencyHist[t]; }
109
110    Stats::Histogram& getHitLatencyHist() { return m_hitLatencyHist; }
111    Stats::Histogram& getHitTypeLatencyHist(uint32_t t)
112    { return *m_hitTypeLatencyHist[t]; }
113
114    Stats::Histogram& getHitMachLatencyHist(uint32_t t)
115    { return *m_hitMachLatencyHist[t]; }
116
117    Stats::Histogram& getHitTypeMachLatencyHist(uint32_t r, uint32_t t)
118    { return *m_hitTypeMachLatencyHist[r][t]; }
119
120    Stats::Histogram& getMissLatencyHist()
121    { return m_missLatencyHist; }
122    Stats::Histogram& getMissTypeLatencyHist(uint32_t t)
123    { return *m_missTypeLatencyHist[t]; }
124
125    Stats::Histogram& getMissMachLatencyHist(uint32_t t) const
126    { return *m_missMachLatencyHist[t]; }
127
128    Stats::Histogram&
129    getMissTypeMachLatencyHist(uint32_t r, uint32_t t) const
130    { return *m_missTypeMachLatencyHist[r][t]; }
131
132    Stats::Histogram& getIssueToInitialDelayHist(uint32_t t) const
133    { return *m_IssueToInitialDelayHist[t]; }
134
135    Stats::Histogram&
136    getInitialToForwardDelayHist(const MachineType t) const
137    { return *m_InitialToForwardDelayHist[t]; }
138
139    Stats::Histogram&
140    getForwardRequestToFirstResponseHist(const MachineType t) const
141    { return *m_ForwardToFirstResponseDelayHist[t]; }
142
143    Stats::Histogram&
144    getFirstResponseToCompletionDelayHist(const MachineType t) const
145    { return *m_FirstResponseToCompletionDelayHist[t]; }
146
147    Stats::Counter getIncompleteTimes(const MachineType t) const
148    { return m_IncompleteTimes[t]; }
149
150  private:
151    void issueRequest(PacketPtr pkt, RubyRequestType type);
152
153    void hitCallback(SequencerRequest* request, DataBlock& data,
154                     bool llscSuccess,
155                     const MachineType mach, const bool externalHit,
156                     const Cycles initialRequestTime,
157                     const Cycles forwardRequestTime,
158                     const Cycles firstResponseTime);
159
160    void recordMissLatency(const Cycles t, const RubyRequestType type,
161                           const MachineType respondingMach,
162                           bool isExternalHit, Cycles issuedTime,
163                           Cycles initialRequestTime,
164                           Cycles forwardRequestTime, Cycles firstResponseTime,
165                           Cycles completionTime);
166
167    RequestStatus insertRequest(PacketPtr pkt, RubyRequestType request_type);
168    bool handleLlsc(Addr address, SequencerRequest* request);
169
170    // Private copy constructor and assignment operator
171    Sequencer(const Sequencer& obj);
172    Sequencer& operator=(const Sequencer& obj);
173
174  private:
175    int m_max_outstanding_requests;
176    Cycles m_deadlock_threshold;
177
178    CacheMemory* m_dataCache_ptr;
179    CacheMemory* m_instCache_ptr;
180
181    // The cache access latency for top-level caches (L0/L1). These are
182    // currently assessed at the beginning of each memory access through the
183    // sequencer.
184    // TODO: Migrate these latencies into top-level cache controllers.
185    Cycles m_data_cache_hit_latency;
186    Cycles m_inst_cache_hit_latency;
187
188    typedef std::unordered_map<Addr, SequencerRequest*> RequestTable;
189    RequestTable m_writeRequestTable;
190    RequestTable m_readRequestTable;
191    // Global outstanding request count, across all request tables
192    int m_outstanding_count;
193    bool m_deadlock_check_scheduled;
194
195    //! Counters for recording aliasing information.
196    Stats::Scalar m_store_waiting_on_load;
197    Stats::Scalar m_store_waiting_on_store;
198    Stats::Scalar m_load_waiting_on_store;
199    Stats::Scalar m_load_waiting_on_load;
200
201    bool m_usingNetworkTester;
202
203    //! Histogram for number of outstanding requests per cycle.
204    Stats::Histogram m_outstandReqHist;
205
206    //! Histogram for holding latency profile of all requests.
207    Stats::Histogram m_latencyHist;
208    std::vector<Stats::Histogram *> m_typeLatencyHist;
209
210    //! Histogram for holding latency profile of all requests that
211    //! hit in the controller connected to this sequencer.
212    Stats::Histogram m_hitLatencyHist;
213    std::vector<Stats::Histogram *> m_hitTypeLatencyHist;
214
215    //! Histograms for profiling the latencies for requests that
216    //! did not required external messages.
217    std::vector<Stats::Histogram *> m_hitMachLatencyHist;
218    std::vector< std::vector<Stats::Histogram *> > m_hitTypeMachLatencyHist;
219
220    //! Histogram for holding latency profile of all requests that
221    //! miss in the controller connected to this sequencer.
222    Stats::Histogram m_missLatencyHist;
223    std::vector<Stats::Histogram *> m_missTypeLatencyHist;
224
225    //! Histograms for profiling the latencies for requests that
226    //! required external messages.
227    std::vector<Stats::Histogram *> m_missMachLatencyHist;
228    std::vector< std::vector<Stats::Histogram *> > m_missTypeMachLatencyHist;
229
230    //! Histograms for recording the breakdown of miss latency
231    std::vector<Stats::Histogram *> m_IssueToInitialDelayHist;
232    std::vector<Stats::Histogram *> m_InitialToForwardDelayHist;
233    std::vector<Stats::Histogram *> m_ForwardToFirstResponseDelayHist;
234    std::vector<Stats::Histogram *> m_FirstResponseToCompletionDelayHist;
235    std::vector<Stats::Counter> m_IncompleteTimes;
236
237
238    class SequencerWakeupEvent : public Event
239    {
240      private:
241        Sequencer *m_sequencer_ptr;
242
243      public:
244        SequencerWakeupEvent(Sequencer *_seq) : m_sequencer_ptr(_seq) {}
245        void process() { m_sequencer_ptr->wakeup(); }
246        const char *description() const { return "Sequencer deadlock check"; }
247    };
248
249    SequencerWakeupEvent deadlockCheckEvent;
250};
251
252inline std::ostream&
253operator<<(std::ostream& out, const Sequencer& obj)
254{
255    obj.print(out);
256    out << std::flush;
257    return out;
258}
259
260#endif // __MEM_RUBY_SYSTEM_SEQUENCER_HH__
261