Sequencer.hh revision 11019:fc1e41e88fd3 
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __MEM_RUBY_SYSTEM_SEQUENCER_HH__
30#define __MEM_RUBY_SYSTEM_SEQUENCER_HH__
31
32#include <iostream>
33
34#include "base/hashmap.hh"
35#include "mem/protocol/MachineType.hh"
36#include "mem/protocol/RubyRequestType.hh"
37#include "mem/protocol/SequencerRequestType.hh"
38#include "mem/ruby/common/Address.hh"
39#include "mem/ruby/structures/CacheMemory.hh"
40#include "mem/ruby/system/RubyPort.hh"
41#include "params/RubySequencer.hh"
42
43struct SequencerRequest
44{
45    PacketPtr pkt;
46    RubyRequestType m_type;
47    Cycles issue_time;
48
49    SequencerRequest(PacketPtr _pkt, RubyRequestType _m_type,
50                     Cycles _issue_time)
51        : pkt(_pkt), m_type(_m_type), issue_time(_issue_time)
52    {}
53};
54
55std::ostream& operator<<(std::ostream& out, const SequencerRequest& obj);
56
57class Sequencer : public RubyPort
58{
59  public:
60    typedef RubySequencerParams Params;
61    Sequencer(const Params *);
62    ~Sequencer();
63
64    // Public Methods
65    void wakeup(); // Used only for deadlock detection
66    void printProgress(std::ostream& out) const;
67    void resetStats();
68    void collateStats();
69    void regStats();
70
71    void writeCallback(const Address& address,
72                       DataBlock& data,
73                       const bool externalHit = false,
74                       const MachineType mach = MachineType_NUM,
75                       const Cycles initialRequestTime = Cycles(0),
76                       const Cycles forwardRequestTime = Cycles(0),
77                       const Cycles firstResponseTime = Cycles(0));
78
79    void readCallback(const Address& address,
80                      DataBlock& data,
81                      const bool externalHit = false,
82                      const MachineType mach = MachineType_NUM,
83                      const Cycles initialRequestTime = Cycles(0),
84                      const Cycles forwardRequestTime = Cycles(0),
85                      const Cycles firstResponseTime = Cycles(0));
86
87    RequestStatus makeRequest(PacketPtr pkt);
88    bool empty() const;
89    int outstandingCount() const { return m_outstanding_count; }
90
91    bool isDeadlockEventScheduled() const
92    { return deadlockCheckEvent.scheduled(); }
93
94    void descheduleDeadlockEvent()
95    { deschedule(deadlockCheckEvent); }
96
97    void print(std::ostream& out) const;
98    void checkCoherence(const Address& address);
99
100    void markRemoved();
101    void removeRequest(SequencerRequest* request);
102    void evictionCallback(const Address& address);
103    void invalidateSC(const Address& address);
104
105    void recordRequestType(SequencerRequestType requestType);
106    Stats::Histogram& getOutstandReqHist() { return m_outstandReqHist; }
107
108    Stats::Histogram& getLatencyHist() { return m_latencyHist; }
109    Stats::Histogram& getTypeLatencyHist(uint32_t t)
110    { return *m_typeLatencyHist[t]; }
111
112    Stats::Histogram& getHitLatencyHist() { return m_hitLatencyHist; }
113    Stats::Histogram& getHitTypeLatencyHist(uint32_t t)
114    { return *m_hitTypeLatencyHist[t]; }
115
116    Stats::Histogram& getHitMachLatencyHist(uint32_t t)
117    { return *m_hitMachLatencyHist[t]; }
118
119    Stats::Histogram& getHitTypeMachLatencyHist(uint32_t r, uint32_t t)
120    { return *m_hitTypeMachLatencyHist[r][t]; }
121
122    Stats::Histogram& getMissLatencyHist()
123    { return m_missLatencyHist; }
124    Stats::Histogram& getMissTypeLatencyHist(uint32_t t)
125    { return *m_missTypeLatencyHist[t]; }
126
127    Stats::Histogram& getMissMachLatencyHist(uint32_t t) const
128    { return *m_missMachLatencyHist[t]; }
129
130    Stats::Histogram&
131    getMissTypeMachLatencyHist(uint32_t r, uint32_t t) const
132    { return *m_missTypeMachLatencyHist[r][t]; }
133
134    Stats::Histogram& getIssueToInitialDelayHist(uint32_t t) const
135    { return *m_IssueToInitialDelayHist[t]; }
136
137    Stats::Histogram&
138    getInitialToForwardDelayHist(const MachineType t) const
139    { return *m_InitialToForwardDelayHist[t]; }
140
141    Stats::Histogram&
142    getForwardRequestToFirstResponseHist(const MachineType t) const
143    { return *m_ForwardToFirstResponseDelayHist[t]; }
144
145    Stats::Histogram&
146    getFirstResponseToCompletionDelayHist(const MachineType t) const
147    { return *m_FirstResponseToCompletionDelayHist[t]; }
148
149    Stats::Counter getIncompleteTimes(const MachineType t) const
150    { return m_IncompleteTimes[t]; }
151
152  private:
153    void issueRequest(PacketPtr pkt, RubyRequestType type);
154
155    void hitCallback(SequencerRequest* request, DataBlock& data,
156                     bool llscSuccess,
157                     const MachineType mach, const bool externalHit,
158                     const Cycles initialRequestTime,
159                     const Cycles forwardRequestTime,
160                     const Cycles firstResponseTime);
161
162    void recordMissLatency(const Cycles t, const RubyRequestType type,
163                           const MachineType respondingMach,
164                           bool isExternalHit, Cycles issuedTime,
165                           Cycles initialRequestTime,
166                           Cycles forwardRequestTime, Cycles firstResponseTime,
167                           Cycles completionTime);
168
169    RequestStatus insertRequest(PacketPtr pkt, RubyRequestType request_type);
170    bool handleLlsc(const Address& address, SequencerRequest* request);
171
172    // Private copy constructor and assignment operator
173    Sequencer(const Sequencer& obj);
174    Sequencer& operator=(const Sequencer& obj);
175
176  private:
177    int m_max_outstanding_requests;
178    Cycles m_deadlock_threshold;
179
180    CacheMemory* m_dataCache_ptr;
181    CacheMemory* m_instCache_ptr;
182
183    // The cache access latency for top-level caches (L0/L1). These are
184    // currently assessed at the beginning of each memory access through the
185    // sequencer.
186    // TODO: Migrate these latencies into top-level cache controllers.
187    Cycles m_data_cache_hit_latency;
188    Cycles m_inst_cache_hit_latency;
189
190    typedef m5::hash_map<Address, SequencerRequest*> RequestTable;
191    RequestTable m_writeRequestTable;
192    RequestTable m_readRequestTable;
193    // Global outstanding request count, across all request tables
194    int m_outstanding_count;
195    bool m_deadlock_check_scheduled;
196
197    //! Counters for recording aliasing information.
198    Stats::Scalar m_store_waiting_on_load;
199    Stats::Scalar m_store_waiting_on_store;
200    Stats::Scalar m_load_waiting_on_store;
201    Stats::Scalar m_load_waiting_on_load;
202
203    bool m_usingNetworkTester;
204
205    //! Histogram for number of outstanding requests per cycle.
206    Stats::Histogram m_outstandReqHist;
207
208    //! Histogram for holding latency profile of all requests.
209    Stats::Histogram m_latencyHist;
210    std::vector<Stats::Histogram *> m_typeLatencyHist;
211
212    //! Histogram for holding latency profile of all requests that
213    //! hit in the controller connected to this sequencer.
214    Stats::Histogram m_hitLatencyHist;
215    std::vector<Stats::Histogram *> m_hitTypeLatencyHist;
216
217    //! Histograms for profiling the latencies for requests that
218    //! did not required external messages.
219    std::vector<Stats::Histogram *> m_hitMachLatencyHist;
220    std::vector< std::vector<Stats::Histogram *> > m_hitTypeMachLatencyHist;
221
222    //! Histogram for holding latency profile of all requests that
223    //! miss in the controller connected to this sequencer.
224    Stats::Histogram m_missLatencyHist;
225    std::vector<Stats::Histogram *> m_missTypeLatencyHist;
226
227    //! Histograms for profiling the latencies for requests that
228    //! required external messages.
229    std::vector<Stats::Histogram *> m_missMachLatencyHist;
230    std::vector< std::vector<Stats::Histogram *> > m_missTypeMachLatencyHist;
231
232    //! Histograms for recording the breakdown of miss latency
233    std::vector<Stats::Histogram *> m_IssueToInitialDelayHist;
234    std::vector<Stats::Histogram *> m_InitialToForwardDelayHist;
235    std::vector<Stats::Histogram *> m_ForwardToFirstResponseDelayHist;
236    std::vector<Stats::Histogram *> m_FirstResponseToCompletionDelayHist;
237    std::vector<Stats::Counter> m_IncompleteTimes;
238
239
240    class SequencerWakeupEvent : public Event
241    {
242      private:
243        Sequencer *m_sequencer_ptr;
244
245      public:
246        SequencerWakeupEvent(Sequencer *_seq) : m_sequencer_ptr(_seq) {}
247        void process() { m_sequencer_ptr->wakeup(); }
248        const char *description() const { return "Sequencer deadlock check"; }
249    };
250
251    SequencerWakeupEvent deadlockCheckEvent;
252};
253
254inline std::ostream&
255operator<<(std::ostream& out, const Sequencer& obj)
256{
257    obj.print(out);
258    out << std::flush;
259    return out;
260}
261
262#endif // __MEM_RUBY_SYSTEM_SEQUENCER_HH__
263