Sequencer.hh revision 7055
13115SN/A/* 24125SN/A * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 33115SN/A * All rights reserved. 43115SN/A * 53115SN/A * Redistribution and use in source and binary forms, with or without 63115SN/A * modification, are permitted provided that the following conditions are 73115SN/A * met: redistributions of source code must retain the above copyright 83115SN/A * notice, this list of conditions and the following disclaimer; 93115SN/A * redistributions in binary form must reproduce the above copyright 103115SN/A * notice, this list of conditions and the following disclaimer in the 113115SN/A * documentation and/or other materials provided with the distribution; 123115SN/A * neither the name of the copyright holders nor the names of its 133115SN/A * contributors may be used to endorse or promote products derived from 143115SN/A * this software without specific prior written permission. 153115SN/A * 163115SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173115SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183115SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193115SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203115SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213115SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223115SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233115SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243115SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253115SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263115SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273115SN/A */ 283115SN/A 293115SN/A#ifndef __MEM_RUBY_SYSTEM_SEQUENCER_HH__ 303115SN/A#define __MEM_RUBY_SYSTEM_SEQUENCER_HH__ 313115SN/A 323115SN/A#include <iostream> 333115SN/A 348113Sgblack@eecs.umich.edu#include "mem/gems_common/Map.hh" 353115SN/A#include "mem/protocol/AccessModeType.hh" 363115SN/A#include "mem/protocol/CacheRequestType.hh" 373115SN/A#include "mem/protocol/GenericMachineType.hh" 388108SN/A#include "mem/protocol/PrefetchBit.hh" 398108SN/A#include "mem/ruby/common/Address.hh" 408108SN/A#include "mem/ruby/common/Consumer.hh" 418108SN/A#include "mem/ruby/common/Global.hh" 428108SN/A#include "mem/ruby/system/RubyPort.hh" 438108SN/A 448108SN/Aclass DataBlock; 458108SN/Aclass CacheMsg; 468108SN/Aclass MachineID; 478108SN/Aclass CacheMemory; 488108SN/A 498108SN/Aclass RubySequencerParams; 508108SN/A 518108SN/Astruct SequencerRequest 528108SN/A{ 538108SN/A RubyRequest ruby_request; 548108SN/A Time issue_time; 558108SN/A 568108SN/A SequencerRequest(const RubyRequest & _ruby_request, Time _issue_time) 578108SN/A : ruby_request(_ruby_request), issue_time(_issue_time) 583115SN/A {} 593115SN/A}; 603115SN/A 613115SN/Astd::ostream& operator<<(std::ostream& out, const SequencerRequest& obj); 623115SN/A 63class Sequencer : public RubyPort, public Consumer 64{ 65 public: 66 typedef RubySequencerParams Params; 67 Sequencer(const Params *); 68 ~Sequencer(); 69 70 // Public Methods 71 void wakeup(); // Used only for deadlock detection 72 73 void printConfig(std::ostream& out) const; 74 75 void printProgress(std::ostream& out) const; 76 77 void writeCallback(const Address& address, DataBlock& data); 78 void readCallback(const Address& address, DataBlock& data); 79 80 RequestStatus makeRequest(const RubyRequest & request); 81 RequestStatus getRequestStatus(const RubyRequest& request); 82 bool empty() const; 83 84 void print(std::ostream& out) const; 85 void printStats(std::ostream& out) const; 86 void checkCoherence(const Address& address); 87 88 void removeRequest(SequencerRequest* request); 89 90 private: 91 bool tryCacheAccess(const Address& addr, CacheRequestType type, 92 const Address& pc, AccessModeType access_mode, 93 int size, DataBlock*& data_ptr); 94 void issueRequest(const RubyRequest& request); 95 96 void hitCallback(SequencerRequest* request, DataBlock& data); 97 bool insertRequest(SequencerRequest* request); 98 99 100 // Private copy constructor and assignment operator 101 Sequencer(const Sequencer& obj); 102 Sequencer& operator=(const Sequencer& obj); 103 104 private: 105 int m_max_outstanding_requests; 106 int m_deadlock_threshold; 107 108 CacheMemory* m_dataCache_ptr; 109 CacheMemory* m_instCache_ptr; 110 111 Map<Address, SequencerRequest*> m_writeRequestTable; 112 Map<Address, SequencerRequest*> m_readRequestTable; 113 // Global outstanding request count, across all request tables 114 int m_outstanding_count; 115 bool m_deadlock_check_scheduled; 116 117 int m_store_waiting_on_load_cycles; 118 int m_store_waiting_on_store_cycles; 119 int m_load_waiting_on_store_cycles; 120 int m_load_waiting_on_load_cycles; 121 122 bool m_usingRubyTester; 123 124 class SequencerWakeupEvent : public Event 125 { 126 private: 127 Sequencer *m_sequencer_ptr; 128 129 public: 130 SequencerWakeupEvent(Sequencer *_seq) : m_sequencer_ptr(_seq) {} 131 void process() { m_sequencer_ptr->wakeup(); } 132 const char *description() const { return "Sequencer deadlock check"; } 133 }; 134 135 SequencerWakeupEvent deadlockCheckEvent; 136}; 137 138inline std::ostream& 139operator<<(std::ostream& out, const Sequencer& obj) 140{ 141 obj.print(out); 142 out << std::flush; 143 return out; 144} 145 146#endif // __MEM_RUBY_SYSTEM_SEQUENCER_HH__ 147 148