Sequencer.hh revision 6876
18442Sgblack@eecs.umich.edu 28442Sgblack@eecs.umich.edu/* 311328Ssteve.reinhardt@amd.com * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 48442Sgblack@eecs.umich.edu * All rights reserved. 58442Sgblack@eecs.umich.edu * 68442Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 78442Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 88442Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 98442Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 108442Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 118442Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 128442Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 138442Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 148442Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 158442Sgblack@eecs.umich.edu * this software without specific prior written permission. 168442Sgblack@eecs.umich.edu * 178442Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 188442Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 198442Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 208442Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 218442Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 228442Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 238442Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 248442Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 258442Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 268442Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 278442Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 288442Sgblack@eecs.umich.edu */ 298442Sgblack@eecs.umich.edu 308442Sgblack@eecs.umich.edu/* 318442Sgblack@eecs.umich.edu * $Id: Sequencer.hh 1.70 2006/09/27 14:56:41-05:00 bobba@s1-01.cs.wisc.edu $ 328442Sgblack@eecs.umich.edu * 338442Sgblack@eecs.umich.edu * Description: 348442Sgblack@eecs.umich.edu * 3511328Ssteve.reinhardt@amd.com */ 3611328Ssteve.reinhardt@amd.com 378442Sgblack@eecs.umich.edu#ifndef SEQUENCER_H 3812234Sgabeblack@google.com#define SEQUENCER_H 398442Sgblack@eecs.umich.edu 408442Sgblack@eecs.umich.edu#include "mem/ruby/common/Global.hh" 418442Sgblack@eecs.umich.edu#include "mem/ruby/common/Consumer.hh" 428442Sgblack@eecs.umich.edu#include "mem/protocol/CacheRequestType.hh" 438442Sgblack@eecs.umich.edu#include "mem/protocol/AccessModeType.hh" 448442Sgblack@eecs.umich.edu#include "mem/protocol/GenericMachineType.hh" 4511303Ssteve.reinhardt@amd.com#include "mem/protocol/PrefetchBit.hh" 4612234Sgabeblack@google.com#include "mem/ruby/system/RubyPort.hh" 4712234Sgabeblack@google.com#include "mem/gems_common/Map.hh" 4811608Snikos.nikoleris@arm.com#include "mem/ruby/common/Address.hh" 498442Sgblack@eecs.umich.edu 5011303Ssteve.reinhardt@amd.comclass DataBlock; 518442Sgblack@eecs.umich.educlass CacheMsg; 528442Sgblack@eecs.umich.educlass MachineID; 5311328Ssteve.reinhardt@amd.comclass CacheMemory; 5411328Ssteve.reinhardt@amd.com 5511328Ssteve.reinhardt@amd.comclass RubySequencerParams; 568442Sgblack@eecs.umich.edu 578442Sgblack@eecs.umich.edustruct SequencerRequest { 588442Sgblack@eecs.umich.edu RubyRequest ruby_request; 598442Sgblack@eecs.umich.edu int64_t id; 608442Sgblack@eecs.umich.edu Time issue_time; 618442Sgblack@eecs.umich.edu 628442Sgblack@eecs.umich.edu SequencerRequest(const RubyRequest & _ruby_request, int64_t _id, Time _issue_time) 638442Sgblack@eecs.umich.edu : ruby_request(_ruby_request), id(_id), issue_time(_issue_time) 648442Sgblack@eecs.umich.edu {} 658442Sgblack@eecs.umich.edu}; 668442Sgblack@eecs.umich.edu 678442Sgblack@eecs.umich.edustd::ostream& operator<<(std::ostream& out, const SequencerRequest& obj); 688442Sgblack@eecs.umich.edu 698442Sgblack@eecs.umich.educlass Sequencer : public RubyPort, public Consumer { 708442Sgblack@eecs.umich.edupublic: 718442Sgblack@eecs.umich.edu typedef RubySequencerParams Params; 728442Sgblack@eecs.umich.edu // Constructors 738442Sgblack@eecs.umich.edu Sequencer(const Params *); 748442Sgblack@eecs.umich.edu 758442Sgblack@eecs.umich.edu // Destructor 768442Sgblack@eecs.umich.edu ~Sequencer(); 7712384Sgabeblack@google.com 7812384Sgabeblack@google.com // Public Methods 7912384Sgabeblack@google.com void wakeup(); // Used only for deadlock detection 8012384Sgabeblack@google.com 8112384Sgabeblack@google.com void printConfig(ostream& out) const; 8212384Sgabeblack@google.com 8312384Sgabeblack@google.com void printProgress(ostream& out) const; 8412384Sgabeblack@google.com 8511328Ssteve.reinhardt@amd.com void writeCallback(const Address& address, DataBlock& data); 8611328Ssteve.reinhardt@amd.com void readCallback(const Address& address, DataBlock& data); 8712384Sgabeblack@google.com 8811328Ssteve.reinhardt@amd.com // called by Tester or Simics 8911328Ssteve.reinhardt@amd.com int64_t makeRequest(const RubyRequest & request); 9011328Ssteve.reinhardt@amd.com int isReady(const RubyRequest& request); 9112384Sgabeblack@google.com bool empty() const; 9212384Sgabeblack@google.com 9312384Sgabeblack@google.com void print(ostream& out) const; 9412384Sgabeblack@google.com void printStats(ostream & out) const; 9512384Sgabeblack@google.com void checkCoherence(const Address& address); 9612384Sgabeblack@google.com 9712384Sgabeblack@google.com // bool getRubyMemoryValue(const Address& addr, char* value, unsigned int size_in_bytes); 9812384Sgabeblack@google.com // bool setRubyMemoryValue(const Address& addr, char *value, unsigned int size_in_bytes); 9912384Sgabeblack@google.com 10012384Sgabeblack@google.com void removeRequest(SequencerRequest* request); 10111328Ssteve.reinhardt@amd.comprivate: 10211328Ssteve.reinhardt@amd.com // Private Methods 10311328Ssteve.reinhardt@amd.com bool tryCacheAccess(const Address& addr, CacheRequestType type, const Address& pc, AccessModeType access_mode, int size, DataBlock*& data_ptr); 10411328Ssteve.reinhardt@amd.com void issueRequest(const RubyRequest& request); 10511328Ssteve.reinhardt@amd.com 10612234Sgabeblack@google.com void hitCallback(SequencerRequest* request, DataBlock& data); 10712234Sgabeblack@google.com bool insertRequest(SequencerRequest* request); 10812234Sgabeblack@google.com 1098442Sgblack@eecs.umich.edu 1108442Sgblack@eecs.umich.edu // Private copy constructor and assignment operator 11111301Ssteve.reinhardt@amd.com Sequencer(const Sequencer& obj); 1128442Sgblack@eecs.umich.edu Sequencer& operator=(const Sequencer& obj); 1138442Sgblack@eecs.umich.edu 1148442Sgblack@eecs.umich.eduprivate: 1158442Sgblack@eecs.umich.edu int m_max_outstanding_requests; 1168442Sgblack@eecs.umich.edu int m_deadlock_threshold; 1178442Sgblack@eecs.umich.edu 1188442Sgblack@eecs.umich.edu CacheMemory* m_dataCache_ptr; 1198442Sgblack@eecs.umich.edu CacheMemory* m_instCache_ptr; 1208442Sgblack@eecs.umich.edu 1218442Sgblack@eecs.umich.edu // indicates what processor on the chip this sequencer is associated with 1228442Sgblack@eecs.umich.edu int m_controller_type; 12312384Sgabeblack@google.com 12412384Sgabeblack@google.com Map<Address, SequencerRequest*> m_writeRequestTable; 12512384Sgabeblack@google.com Map<Address, SequencerRequest*> m_readRequestTable; 12612384Sgabeblack@google.com // Global outstanding request count, across all request tables 12712384Sgabeblack@google.com int m_outstanding_count; 12812384Sgabeblack@google.com bool m_deadlock_check_scheduled; 12912384Sgabeblack@google.com 13012384Sgabeblack@google.com int m_store_waiting_on_load_cycles; 13112384Sgabeblack@google.com int m_store_waiting_on_store_cycles; 13212384Sgabeblack@google.com int m_load_waiting_on_store_cycles; 13312384Sgabeblack@google.com int m_load_waiting_on_load_cycles; 13412384Sgabeblack@google.com}; 13512384Sgabeblack@google.com 13612384Sgabeblack@google.com// Output operator declaration 13712384Sgabeblack@google.comostream& operator<<(ostream& out, const Sequencer& obj); 13812384Sgabeblack@google.com 13912234Sgabeblack@google.com// ******************* Definitions ******************* 14012384Sgabeblack@google.com 14112234Sgabeblack@google.com// Output operator definition 14211328Ssteve.reinhardt@amd.comextern inline 14311328Ssteve.reinhardt@amd.comostream& operator<<(ostream& out, const Sequencer& obj) 14411328Ssteve.reinhardt@amd.com{ 14512384Sgabeblack@google.com obj.print(out); 14611328Ssteve.reinhardt@amd.com out << flush; 14712384Sgabeblack@google.com return out; 14812384Sgabeblack@google.com} 14912384Sgabeblack@google.com 15012384Sgabeblack@google.com#endif //SEQUENCER_H 15112384Sgabeblack@google.com 15212384Sgabeblack@google.com