Sequencer.hh revision 11168
16145Snate@binkert.org/* 26145Snate@binkert.org * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 36145Snate@binkert.org * All rights reserved. 46145Snate@binkert.org * 56145Snate@binkert.org * Redistribution and use in source and binary forms, with or without 66145Snate@binkert.org * modification, are permitted provided that the following conditions are 76145Snate@binkert.org * met: redistributions of source code must retain the above copyright 86145Snate@binkert.org * notice, this list of conditions and the following disclaimer; 96145Snate@binkert.org * redistributions in binary form must reproduce the above copyright 106145Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 116145Snate@binkert.org * documentation and/or other materials provided with the distribution; 126145Snate@binkert.org * neither the name of the copyright holders nor the names of its 136145Snate@binkert.org * contributors may be used to endorse or promote products derived from 146145Snate@binkert.org * this software without specific prior written permission. 156145Snate@binkert.org * 166145Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176145Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186145Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196145Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206145Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216145Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226145Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236145Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246145Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256145Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266145Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276145Snate@binkert.org */ 286145Snate@binkert.org 297039Snate@binkert.org#ifndef __MEM_RUBY_SYSTEM_SEQUENCER_HH__ 307039Snate@binkert.org#define __MEM_RUBY_SYSTEM_SEQUENCER_HH__ 316145Snate@binkert.org 327055Snate@binkert.org#include <iostream> 3311168Sandreas.hansson@arm.com#include <unordered_map> 347055Snate@binkert.org 359773Snilay@cs.wisc.edu#include "mem/protocol/MachineType.hh" 368165Snilay@cs.wisc.edu#include "mem/protocol/RubyRequestType.hh" 379104Shestness@cs.utexas.edu#include "mem/protocol/SequencerRequestType.hh" 387039Snate@binkert.org#include "mem/ruby/common/Address.hh" 3910301Snilay@cs.wisc.edu#include "mem/ruby/structures/CacheMemory.hh" 406285Snate@binkert.org#include "mem/ruby/system/RubyPort.hh" 419171Snilay@cs.wisc.edu#include "params/RubySequencer.hh" 426145Snate@binkert.org 437039Snate@binkert.orgstruct SequencerRequest 447039Snate@binkert.org{ 458615Snilay@cs.wisc.edu PacketPtr pkt; 468615Snilay@cs.wisc.edu RubyRequestType m_type; 479501Snilay@cs.wisc.edu Cycles issue_time; 486285Snate@binkert.org 499501Snilay@cs.wisc.edu SequencerRequest(PacketPtr _pkt, RubyRequestType _m_type, 509501Snilay@cs.wisc.edu Cycles _issue_time) 518615Snilay@cs.wisc.edu : pkt(_pkt), m_type(_m_type), issue_time(_issue_time) 527039Snate@binkert.org {} 536285Snate@binkert.org}; 546285Snate@binkert.org 556763SBrad.Beckmann@amd.comstd::ostream& operator<<(std::ostream& out, const SequencerRequest& obj); 566763SBrad.Beckmann@amd.com 579171Snilay@cs.wisc.educlass Sequencer : public RubyPort 587039Snate@binkert.org{ 597039Snate@binkert.org public: 606876Ssteve.reinhardt@amd.com typedef RubySequencerParams Params; 617039Snate@binkert.org Sequencer(const Params *); 627039Snate@binkert.org ~Sequencer(); 636145Snate@binkert.org 647039Snate@binkert.org // Public Methods 657039Snate@binkert.org void wakeup(); // Used only for deadlock detection 6610012Snilay@cs.wisc.edu void resetStats(); 6710012Snilay@cs.wisc.edu void collateStats(); 6810012Snilay@cs.wisc.edu void regStats(); 699598Snilay@cs.wisc.edu 7011025Snilay@cs.wisc.edu void writeCallback(Addr address, 717565SBrad.Beckmann@amd.com DataBlock& data, 729773Snilay@cs.wisc.edu const bool externalHit = false, 739773Snilay@cs.wisc.edu const MachineType mach = MachineType_NUM, 749773Snilay@cs.wisc.edu const Cycles initialRequestTime = Cycles(0), 759773Snilay@cs.wisc.edu const Cycles forwardRequestTime = Cycles(0), 769773Snilay@cs.wisc.edu const Cycles firstResponseTime = Cycles(0)); 776145Snate@binkert.org 7811025Snilay@cs.wisc.edu void readCallback(Addr address, 797565SBrad.Beckmann@amd.com DataBlock& data, 809773Snilay@cs.wisc.edu const bool externalHit = false, 819773Snilay@cs.wisc.edu const MachineType mach = MachineType_NUM, 829773Snilay@cs.wisc.edu const Cycles initialRequestTime = Cycles(0), 839773Snilay@cs.wisc.edu const Cycles forwardRequestTime = Cycles(0), 849773Snilay@cs.wisc.edu const Cycles firstResponseTime = Cycles(0)); 857565SBrad.Beckmann@amd.com 868615Snilay@cs.wisc.edu RequestStatus makeRequest(PacketPtr pkt); 877039Snate@binkert.org bool empty() const; 888688Snilay@cs.wisc.edu int outstandingCount() const { return m_outstanding_count; } 898688Snilay@cs.wisc.edu 909598Snilay@cs.wisc.edu bool isDeadlockEventScheduled() const 919598Snilay@cs.wisc.edu { return deadlockCheckEvent.scheduled(); } 929598Snilay@cs.wisc.edu 939598Snilay@cs.wisc.edu void descheduleDeadlockEvent() 949598Snilay@cs.wisc.edu { deschedule(deadlockCheckEvent); } 956145Snate@binkert.org 967055Snate@binkert.org void print(std::ostream& out) const; 9711025Snilay@cs.wisc.edu void checkCoherence(Addr address); 986145Snate@binkert.org 997455Snate@binkert.org void markRemoved(); 10011025Snilay@cs.wisc.edu void evictionCallback(Addr address); 10111025Snilay@cs.wisc.edu void invalidateSC(Addr address); 1026145Snate@binkert.org 1039104Shestness@cs.utexas.edu void recordRequestType(SequencerRequestType requestType); 10410012Snilay@cs.wisc.edu Stats::Histogram& getOutstandReqHist() { return m_outstandReqHist; } 1059104Shestness@cs.utexas.edu 10610012Snilay@cs.wisc.edu Stats::Histogram& getLatencyHist() { return m_latencyHist; } 10710012Snilay@cs.wisc.edu Stats::Histogram& getTypeLatencyHist(uint32_t t) 10810012Snilay@cs.wisc.edu { return *m_typeLatencyHist[t]; } 1099773Snilay@cs.wisc.edu 11010012Snilay@cs.wisc.edu Stats::Histogram& getHitLatencyHist() { return m_hitLatencyHist; } 11110012Snilay@cs.wisc.edu Stats::Histogram& getHitTypeLatencyHist(uint32_t t) 11210012Snilay@cs.wisc.edu { return *m_hitTypeLatencyHist[t]; } 1139773Snilay@cs.wisc.edu 11410012Snilay@cs.wisc.edu Stats::Histogram& getHitMachLatencyHist(uint32_t t) 11510012Snilay@cs.wisc.edu { return *m_hitMachLatencyHist[t]; } 1169773Snilay@cs.wisc.edu 11710012Snilay@cs.wisc.edu Stats::Histogram& getHitTypeMachLatencyHist(uint32_t r, uint32_t t) 11810012Snilay@cs.wisc.edu { return *m_hitTypeMachLatencyHist[r][t]; } 1199773Snilay@cs.wisc.edu 12010012Snilay@cs.wisc.edu Stats::Histogram& getMissLatencyHist() 12110012Snilay@cs.wisc.edu { return m_missLatencyHist; } 12210012Snilay@cs.wisc.edu Stats::Histogram& getMissTypeLatencyHist(uint32_t t) 12310012Snilay@cs.wisc.edu { return *m_missTypeLatencyHist[t]; } 1249773Snilay@cs.wisc.edu 12510012Snilay@cs.wisc.edu Stats::Histogram& getMissMachLatencyHist(uint32_t t) const 12610012Snilay@cs.wisc.edu { return *m_missMachLatencyHist[t]; } 1279773Snilay@cs.wisc.edu 12810012Snilay@cs.wisc.edu Stats::Histogram& 12910012Snilay@cs.wisc.edu getMissTypeMachLatencyHist(uint32_t r, uint32_t t) const 13010012Snilay@cs.wisc.edu { return *m_missTypeMachLatencyHist[r][t]; } 1319773Snilay@cs.wisc.edu 13210012Snilay@cs.wisc.edu Stats::Histogram& getIssueToInitialDelayHist(uint32_t t) const 13310012Snilay@cs.wisc.edu { return *m_IssueToInitialDelayHist[t]; } 1349773Snilay@cs.wisc.edu 13510012Snilay@cs.wisc.edu Stats::Histogram& 13610012Snilay@cs.wisc.edu getInitialToForwardDelayHist(const MachineType t) const 13710012Snilay@cs.wisc.edu { return *m_InitialToForwardDelayHist[t]; } 1389773Snilay@cs.wisc.edu 13910012Snilay@cs.wisc.edu Stats::Histogram& 14010012Snilay@cs.wisc.edu getForwardRequestToFirstResponseHist(const MachineType t) const 14110012Snilay@cs.wisc.edu { return *m_ForwardToFirstResponseDelayHist[t]; } 1429773Snilay@cs.wisc.edu 14310012Snilay@cs.wisc.edu Stats::Histogram& 14410012Snilay@cs.wisc.edu getFirstResponseToCompletionDelayHist(const MachineType t) const 14510012Snilay@cs.wisc.edu { return *m_FirstResponseToCompletionDelayHist[t]; } 1469773Snilay@cs.wisc.edu 14710012Snilay@cs.wisc.edu Stats::Counter getIncompleteTimes(const MachineType t) const 1489773Snilay@cs.wisc.edu { return m_IncompleteTimes[t]; } 1499773Snilay@cs.wisc.edu 1507039Snate@binkert.org private: 1518615Snilay@cs.wisc.edu void issueRequest(PacketPtr pkt, RubyRequestType type); 1526145Snate@binkert.org 1539773Snilay@cs.wisc.edu void hitCallback(SequencerRequest* request, DataBlock& data, 1549773Snilay@cs.wisc.edu bool llscSuccess, 1559773Snilay@cs.wisc.edu const MachineType mach, const bool externalHit, 1569773Snilay@cs.wisc.edu const Cycles initialRequestTime, 1579773Snilay@cs.wisc.edu const Cycles forwardRequestTime, 1589773Snilay@cs.wisc.edu const Cycles firstResponseTime); 1599773Snilay@cs.wisc.edu 1609773Snilay@cs.wisc.edu void recordMissLatency(const Cycles t, const RubyRequestType type, 1619773Snilay@cs.wisc.edu const MachineType respondingMach, 1629773Snilay@cs.wisc.edu bool isExternalHit, Cycles issuedTime, 1639773Snilay@cs.wisc.edu Cycles initialRequestTime, 1649773Snilay@cs.wisc.edu Cycles forwardRequestTime, Cycles firstResponseTime, 1659773Snilay@cs.wisc.edu Cycles completionTime); 1667546SBrad.Beckmann@amd.com 1678615Snilay@cs.wisc.edu RequestStatus insertRequest(PacketPtr pkt, RubyRequestType request_type); 16811025Snilay@cs.wisc.edu bool handleLlsc(Addr address, SequencerRequest* request); 1696145Snate@binkert.org 1707039Snate@binkert.org // Private copy constructor and assignment operator 1717039Snate@binkert.org Sequencer(const Sequencer& obj); 1727039Snate@binkert.org Sequencer& operator=(const Sequencer& obj); 1736145Snate@binkert.org 1747039Snate@binkert.org private: 1757039Snate@binkert.org int m_max_outstanding_requests; 1769184Sandreas.hansson@arm.com Cycles m_deadlock_threshold; 1776145Snate@binkert.org 1787039Snate@binkert.org CacheMemory* m_dataCache_ptr; 1797039Snate@binkert.org CacheMemory* m_instCache_ptr; 1806285Snate@binkert.org 18111019Sjthestness@gmail.com // The cache access latency for top-level caches (L0/L1). These are 18211019Sjthestness@gmail.com // currently assessed at the beginning of each memory access through the 18311019Sjthestness@gmail.com // sequencer. 18411019Sjthestness@gmail.com // TODO: Migrate these latencies into top-level cache controllers. 18511019Sjthestness@gmail.com Cycles m_data_cache_hit_latency; 18611019Sjthestness@gmail.com Cycles m_inst_cache_hit_latency; 18711019Sjthestness@gmail.com 18811168Sandreas.hansson@arm.com typedef std::unordered_map<Addr, SequencerRequest*> RequestTable; 1897455Snate@binkert.org RequestTable m_writeRequestTable; 1907455Snate@binkert.org RequestTable m_readRequestTable; 1917039Snate@binkert.org // Global outstanding request count, across all request tables 1927039Snate@binkert.org int m_outstanding_count; 1937039Snate@binkert.org bool m_deadlock_check_scheduled; 1946145Snate@binkert.org 19510012Snilay@cs.wisc.edu //! Counters for recording aliasing information. 19610012Snilay@cs.wisc.edu Stats::Scalar m_store_waiting_on_load; 19710012Snilay@cs.wisc.edu Stats::Scalar m_store_waiting_on_store; 19810012Snilay@cs.wisc.edu Stats::Scalar m_load_waiting_on_store; 19910012Snilay@cs.wisc.edu Stats::Scalar m_load_waiting_on_load; 2006859Sdrh5@cs.wisc.edu 2018171Stushar@csail.mit.edu bool m_usingNetworkTester; 2028171Stushar@csail.mit.edu 2039598Snilay@cs.wisc.edu //! Histogram for number of outstanding requests per cycle. 20410012Snilay@cs.wisc.edu Stats::Histogram m_outstandReqHist; 2059598Snilay@cs.wisc.edu 2069773Snilay@cs.wisc.edu //! Histogram for holding latency profile of all requests. 20710012Snilay@cs.wisc.edu Stats::Histogram m_latencyHist; 20810012Snilay@cs.wisc.edu std::vector<Stats::Histogram *> m_typeLatencyHist; 2099773Snilay@cs.wisc.edu 2109773Snilay@cs.wisc.edu //! Histogram for holding latency profile of all requests that 2119773Snilay@cs.wisc.edu //! hit in the controller connected to this sequencer. 21210012Snilay@cs.wisc.edu Stats::Histogram m_hitLatencyHist; 21310012Snilay@cs.wisc.edu std::vector<Stats::Histogram *> m_hitTypeLatencyHist; 2149773Snilay@cs.wisc.edu 2159773Snilay@cs.wisc.edu //! Histograms for profiling the latencies for requests that 2169773Snilay@cs.wisc.edu //! did not required external messages. 21710012Snilay@cs.wisc.edu std::vector<Stats::Histogram *> m_hitMachLatencyHist; 21810012Snilay@cs.wisc.edu std::vector< std::vector<Stats::Histogram *> > m_hitTypeMachLatencyHist; 2199773Snilay@cs.wisc.edu 2209773Snilay@cs.wisc.edu //! Histogram for holding latency profile of all requests that 2219773Snilay@cs.wisc.edu //! miss in the controller connected to this sequencer. 22210012Snilay@cs.wisc.edu Stats::Histogram m_missLatencyHist; 22310012Snilay@cs.wisc.edu std::vector<Stats::Histogram *> m_missTypeLatencyHist; 2249773Snilay@cs.wisc.edu 2259773Snilay@cs.wisc.edu //! Histograms for profiling the latencies for requests that 2269773Snilay@cs.wisc.edu //! required external messages. 22710012Snilay@cs.wisc.edu std::vector<Stats::Histogram *> m_missMachLatencyHist; 22810012Snilay@cs.wisc.edu std::vector< std::vector<Stats::Histogram *> > m_missTypeMachLatencyHist; 2299773Snilay@cs.wisc.edu 2309773Snilay@cs.wisc.edu //! Histograms for recording the breakdown of miss latency 23110012Snilay@cs.wisc.edu std::vector<Stats::Histogram *> m_IssueToInitialDelayHist; 23210012Snilay@cs.wisc.edu std::vector<Stats::Histogram *> m_InitialToForwardDelayHist; 23310012Snilay@cs.wisc.edu std::vector<Stats::Histogram *> m_ForwardToFirstResponseDelayHist; 23410012Snilay@cs.wisc.edu std::vector<Stats::Histogram *> m_FirstResponseToCompletionDelayHist; 23510012Snilay@cs.wisc.edu std::vector<Stats::Counter> m_IncompleteTimes; 2369773Snilay@cs.wisc.edu 2379773Snilay@cs.wisc.edu 2387039Snate@binkert.org class SequencerWakeupEvent : public Event 2397039Snate@binkert.org { 2407039Snate@binkert.org private: 2417039Snate@binkert.org Sequencer *m_sequencer_ptr; 2426899SBrad.Beckmann@amd.com 2437039Snate@binkert.org public: 2447039Snate@binkert.org SequencerWakeupEvent(Sequencer *_seq) : m_sequencer_ptr(_seq) {} 2457039Snate@binkert.org void process() { m_sequencer_ptr->wakeup(); } 2467039Snate@binkert.org const char *description() const { return "Sequencer deadlock check"; } 2477039Snate@binkert.org }; 2486886SBrad.Beckmann@amd.com 2497039Snate@binkert.org SequencerWakeupEvent deadlockCheckEvent; 2506145Snate@binkert.org}; 2516145Snate@binkert.org 2527055Snate@binkert.orginline std::ostream& 2537055Snate@binkert.orgoperator<<(std::ostream& out, const Sequencer& obj) 2546145Snate@binkert.org{ 2557039Snate@binkert.org obj.print(out); 2567055Snate@binkert.org out << std::flush; 2577039Snate@binkert.org return out; 2586145Snate@binkert.org} 2596145Snate@binkert.org 2607039Snate@binkert.org#endif // __MEM_RUBY_SYSTEM_SEQUENCER_HH__ 261