Sequencer.cc revision 9563:08d097040f90 
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "base/misc.hh"
30#include "base/str.hh"
31#include "config/the_isa.hh"
32#if THE_ISA == X86_ISA
33#include "arch/x86/insts/microldstop.hh"
34#endif // X86_ISA
35#include "cpu/testers/rubytest/RubyTester.hh"
36#include "debug/MemoryAccess.hh"
37#include "debug/ProtocolTrace.hh"
38#include "debug/RubySequencer.hh"
39#include "debug/RubyStats.hh"
40#include "mem/protocol/PrefetchBit.hh"
41#include "mem/protocol/RubyAccessMode.hh"
42#include "mem/ruby/common/Global.hh"
43#include "mem/ruby/profiler/Profiler.hh"
44#include "mem/ruby/slicc_interface/RubyRequest.hh"
45#include "mem/ruby/system/Sequencer.hh"
46#include "mem/ruby/system/System.hh"
47#include "mem/packet.hh"
48
49using namespace std;
50
51Sequencer *
52RubySequencerParams::create()
53{
54    return new Sequencer(this);
55}
56
57Sequencer::Sequencer(const Params *p)
58    : RubyPort(p), deadlockCheckEvent(this)
59{
60    m_store_waiting_on_load_cycles = 0;
61    m_store_waiting_on_store_cycles = 0;
62    m_load_waiting_on_store_cycles = 0;
63    m_load_waiting_on_load_cycles = 0;
64
65    m_outstanding_count = 0;
66
67    m_instCache_ptr = p->icache;
68    m_dataCache_ptr = p->dcache;
69    m_max_outstanding_requests = p->max_outstanding_requests;
70    m_deadlock_threshold = p->deadlock_threshold;
71
72    assert(m_max_outstanding_requests > 0);
73    assert(m_deadlock_threshold > 0);
74    assert(m_instCache_ptr != NULL);
75    assert(m_dataCache_ptr != NULL);
76
77    m_usingNetworkTester = p->using_network_tester;
78}
79
80Sequencer::~Sequencer()
81{
82}
83
84void
85Sequencer::wakeup()
86{
87    assert(getDrainState() != Drainable::Draining);
88
89    // Check for deadlock of any of the requests
90    Cycles current_time = curCycle();
91
92    // Check across all outstanding requests
93    int total_outstanding = 0;
94
95    RequestTable::iterator read = m_readRequestTable.begin();
96    RequestTable::iterator read_end = m_readRequestTable.end();
97    for (; read != read_end; ++read) {
98        SequencerRequest* request = read->second;
99        if (current_time - request->issue_time < m_deadlock_threshold)
100            continue;
101
102        panic("Possible Deadlock detected. Aborting!\n"
103             "version: %d request.paddr: 0x%x m_readRequestTable: %d "
104             "current time: %u issue_time: %d difference: %d\n", m_version,
105             Address(request->pkt->getAddr()), m_readRequestTable.size(),
106              current_time * clockPeriod(), request->issue_time * clockPeriod(),
107              (current_time * clockPeriod()) - (request->issue_time * clockPeriod()));
108    }
109
110    RequestTable::iterator write = m_writeRequestTable.begin();
111    RequestTable::iterator write_end = m_writeRequestTable.end();
112    for (; write != write_end; ++write) {
113        SequencerRequest* request = write->second;
114        if (current_time - request->issue_time < m_deadlock_threshold)
115            continue;
116
117        panic("Possible Deadlock detected. Aborting!\n"
118             "version: %d request.paddr: 0x%x m_writeRequestTable: %d "
119             "current time: %u issue_time: %d difference: %d\n", m_version,
120             Address(request->pkt->getAddr()), m_writeRequestTable.size(),
121              current_time * clockPeriod(), request->issue_time * clockPeriod(),
122              (current_time * clockPeriod()) - (request->issue_time * clockPeriod()));
123    }
124
125    total_outstanding += m_writeRequestTable.size();
126    total_outstanding += m_readRequestTable.size();
127
128    assert(m_outstanding_count == total_outstanding);
129
130    if (m_outstanding_count > 0) {
131        // If there are still outstanding requests, keep checking
132        schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold));
133    }
134}
135
136void
137Sequencer::printStats(ostream & out) const
138{
139    out << "Sequencer: " << m_name << endl
140        << "  store_waiting_on_load_cycles: "
141        << m_store_waiting_on_load_cycles << endl
142        << "  store_waiting_on_store_cycles: "
143        << m_store_waiting_on_store_cycles << endl
144        << "  load_waiting_on_load_cycles: "
145        << m_load_waiting_on_load_cycles << endl
146        << "  load_waiting_on_store_cycles: "
147        << m_load_waiting_on_store_cycles << endl;
148}
149
150void
151Sequencer::printProgress(ostream& out) const
152{
153#if 0
154    int total_demand = 0;
155    out << "Sequencer Stats Version " << m_version << endl;
156    out << "Current time = " << g_system_ptr->getTime() << endl;
157    out << "---------------" << endl;
158    out << "outstanding requests" << endl;
159
160    out << "proc " << m_Read
161        << " version Requests = " << m_readRequestTable.size() << endl;
162
163    // print the request table
164    RequestTable::iterator read = m_readRequestTable.begin();
165    RequestTable::iterator read_end = m_readRequestTable.end();
166    for (; read != read_end; ++read) {
167        SequencerRequest* request = read->second;
168        out << "\tRequest[ " << i << " ] = " << request->type
169            << " Address " << rkeys[i]
170            << " Posted " << request->issue_time
171            << " PF " << PrefetchBit_No << endl;
172        total_demand++;
173    }
174
175    out << "proc " << m_version
176        << " Write Requests = " << m_writeRequestTable.size << endl;
177
178    // print the request table
179    RequestTable::iterator write = m_writeRequestTable.begin();
180    RequestTable::iterator write_end = m_writeRequestTable.end();
181    for (; write != write_end; ++write) {
182        SequencerRequest* request = write->second;
183        out << "\tRequest[ " << i << " ] = " << request.getType()
184            << " Address " << wkeys[i]
185            << " Posted " << request.getTime()
186            << " PF " << request.getPrefetch() << endl;
187        if (request.getPrefetch() == PrefetchBit_No) {
188            total_demand++;
189        }
190    }
191
192    out << endl;
193
194    out << "Total Number Outstanding: " << m_outstanding_count << endl
195        << "Total Number Demand     : " << total_demand << endl
196        << "Total Number Prefetches : " << m_outstanding_count - total_demand
197        << endl << endl << endl;
198#endif
199}
200
201// Insert the request on the correct request table.  Return true if
202// the entry was already present.
203RequestStatus
204Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
205{
206    assert(m_outstanding_count ==
207        (m_writeRequestTable.size() + m_readRequestTable.size()));
208
209    // See if we should schedule a deadlock check
210    if (!deadlockCheckEvent.scheduled() &&
211        getDrainState() != Drainable::Draining) {
212        schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold));
213    }
214
215    Address line_addr(pkt->getAddr());
216    line_addr.makeLineAddress();
217    // Create a default entry, mapping the address to NULL, the cast is
218    // there to make gcc 4.4 happy
219    RequestTable::value_type default_entry(line_addr,
220                                           (SequencerRequest*) NULL);
221
222    if ((request_type == RubyRequestType_ST) ||
223        (request_type == RubyRequestType_RMW_Read) ||
224        (request_type == RubyRequestType_RMW_Write) ||
225        (request_type == RubyRequestType_Load_Linked) ||
226        (request_type == RubyRequestType_Store_Conditional) ||
227        (request_type == RubyRequestType_Locked_RMW_Read) ||
228        (request_type == RubyRequestType_Locked_RMW_Write) ||
229        (request_type == RubyRequestType_FLUSH)) {
230
231        // Check if there is any outstanding read request for the same
232        // cache line.
233        if (m_readRequestTable.count(line_addr) > 0) {
234            m_store_waiting_on_load_cycles++;
235            return RequestStatus_Aliased;
236        }
237
238        pair<RequestTable::iterator, bool> r =
239            m_writeRequestTable.insert(default_entry);
240        if (r.second) {
241            RequestTable::iterator i = r.first;
242            i->second = new SequencerRequest(pkt, request_type, curCycle());
243            m_outstanding_count++;
244        } else {
245          // There is an outstanding write request for the cache line
246          m_store_waiting_on_store_cycles++;
247          return RequestStatus_Aliased;
248        }
249    } else {
250        // Check if there is any outstanding write request for the same
251        // cache line.
252        if (m_writeRequestTable.count(line_addr) > 0) {
253            m_load_waiting_on_store_cycles++;
254            return RequestStatus_Aliased;
255        }
256
257        pair<RequestTable::iterator, bool> r =
258            m_readRequestTable.insert(default_entry);
259
260        if (r.second) {
261            RequestTable::iterator i = r.first;
262            i->second = new SequencerRequest(pkt, request_type, curCycle());
263            m_outstanding_count++;
264        } else {
265            // There is an outstanding read request for the cache line
266            m_load_waiting_on_load_cycles++;
267            return RequestStatus_Aliased;
268        }
269    }
270
271    g_system_ptr->getProfiler()->sequencerRequests(m_outstanding_count);
272    assert(m_outstanding_count ==
273        (m_writeRequestTable.size() + m_readRequestTable.size()));
274
275    return RequestStatus_Ready;
276}
277
278void
279Sequencer::markRemoved()
280{
281    m_outstanding_count--;
282    assert(m_outstanding_count ==
283           m_writeRequestTable.size() + m_readRequestTable.size());
284}
285
286void
287Sequencer::removeRequest(SequencerRequest* srequest)
288{
289    assert(m_outstanding_count ==
290           m_writeRequestTable.size() + m_readRequestTable.size());
291
292    Address line_addr(srequest->pkt->getAddr());
293    line_addr.makeLineAddress();
294    if ((srequest->m_type == RubyRequestType_ST) ||
295        (srequest->m_type == RubyRequestType_RMW_Read) ||
296        (srequest->m_type == RubyRequestType_RMW_Write) ||
297        (srequest->m_type == RubyRequestType_Load_Linked) ||
298        (srequest->m_type == RubyRequestType_Store_Conditional) ||
299        (srequest->m_type == RubyRequestType_Locked_RMW_Read) ||
300        (srequest->m_type == RubyRequestType_Locked_RMW_Write)) {
301        m_writeRequestTable.erase(line_addr);
302    } else {
303        m_readRequestTable.erase(line_addr);
304    }
305
306    markRemoved();
307}
308
309void
310Sequencer::invalidateSC(const Address& address)
311{
312    RequestTable::iterator i = m_writeRequestTable.find(address);
313    if (i != m_writeRequestTable.end()) {
314        SequencerRequest* request = i->second;
315        // The controller has lost the coherence permissions, hence the lock
316        // on the cache line maintained by the cache should be cleared.
317        if (request->m_type == RubyRequestType_Store_Conditional) {
318            m_dataCache_ptr->clearLocked(address);
319        }
320    }
321}
322
323bool
324Sequencer::handleLlsc(const Address& address, SequencerRequest* request)
325{
326    //
327    // The success flag indicates whether the LLSC operation was successful.
328    // LL ops will always succeed, but SC may fail if the cache line is no
329    // longer locked.
330    //
331    bool success = true;
332    if (request->m_type == RubyRequestType_Store_Conditional) {
333        if (!m_dataCache_ptr->isLocked(address, m_version)) {
334            //
335            // For failed SC requests, indicate the failure to the cpu by
336            // setting the extra data to zero.
337            //
338            request->pkt->req->setExtraData(0);
339            success = false;
340        } else {
341            //
342            // For successful SC requests, indicate the success to the cpu by
343            // setting the extra data to one.
344            //
345            request->pkt->req->setExtraData(1);
346        }
347        //
348        // Independent of success, all SC operations must clear the lock
349        //
350        m_dataCache_ptr->clearLocked(address);
351    } else if (request->m_type == RubyRequestType_Load_Linked) {
352        //
353        // Note: To fully follow Alpha LLSC semantics, should the LL clear any
354        // previously locked cache lines?
355        //
356        m_dataCache_ptr->setLocked(address, m_version);
357    } else if ((m_dataCache_ptr->isTagPresent(address)) &&
358               (m_dataCache_ptr->isLocked(address, m_version))) {
359        //
360        // Normal writes should clear the locked address
361        //
362        m_dataCache_ptr->clearLocked(address);
363    }
364    return success;
365}
366
367void
368Sequencer::writeCallback(const Address& address, DataBlock& data)
369{
370    writeCallback(address, GenericMachineType_NULL, data);
371}
372
373void
374Sequencer::writeCallback(const Address& address,
375                         GenericMachineType mach,
376                         DataBlock& data)
377{
378    writeCallback(address, mach, data, Cycles(0), Cycles(0), Cycles(0));
379}
380
381void
382Sequencer::writeCallback(const Address& address,
383                         GenericMachineType mach,
384                         DataBlock& data,
385                         Cycles initialRequestTime,
386                         Cycles forwardRequestTime,
387                         Cycles firstResponseTime)
388{
389    assert(address == line_address(address));
390    assert(m_writeRequestTable.count(line_address(address)));
391
392    RequestTable::iterator i = m_writeRequestTable.find(address);
393    assert(i != m_writeRequestTable.end());
394    SequencerRequest* request = i->second;
395
396    m_writeRequestTable.erase(i);
397    markRemoved();
398
399    assert((request->m_type == RubyRequestType_ST) ||
400           (request->m_type == RubyRequestType_ATOMIC) ||
401           (request->m_type == RubyRequestType_RMW_Read) ||
402           (request->m_type == RubyRequestType_RMW_Write) ||
403           (request->m_type == RubyRequestType_Load_Linked) ||
404           (request->m_type == RubyRequestType_Store_Conditional) ||
405           (request->m_type == RubyRequestType_Locked_RMW_Read) ||
406           (request->m_type == RubyRequestType_Locked_RMW_Write) ||
407           (request->m_type == RubyRequestType_FLUSH));
408
409    //
410    // For Alpha, properly handle LL, SC, and write requests with respect to
411    // locked cache blocks.
412    //
413    // Not valid for Network_test protocl
414    //
415    bool success = true;
416    if(!m_usingNetworkTester)
417        success = handleLlsc(address, request);
418
419    if (request->m_type == RubyRequestType_Locked_RMW_Read) {
420        m_controller->blockOnQueue(address, m_mandatory_q_ptr);
421    } else if (request->m_type == RubyRequestType_Locked_RMW_Write) {
422        m_controller->unblock(address);
423    }
424
425    hitCallback(request, mach, data, success,
426                initialRequestTime, forwardRequestTime, firstResponseTime);
427}
428
429void
430Sequencer::readCallback(const Address& address, DataBlock& data)
431{
432    readCallback(address, GenericMachineType_NULL, data);
433}
434
435void
436Sequencer::readCallback(const Address& address,
437                        GenericMachineType mach,
438                        DataBlock& data)
439{
440    readCallback(address, mach, data, Cycles(0), Cycles(0), Cycles(0));
441}
442
443void
444Sequencer::readCallback(const Address& address,
445                        GenericMachineType mach,
446                        DataBlock& data,
447                        Cycles initialRequestTime,
448                        Cycles forwardRequestTime,
449                        Cycles firstResponseTime)
450{
451    assert(address == line_address(address));
452    assert(m_readRequestTable.count(line_address(address)));
453
454    RequestTable::iterator i = m_readRequestTable.find(address);
455    assert(i != m_readRequestTable.end());
456    SequencerRequest* request = i->second;
457
458    m_readRequestTable.erase(i);
459    markRemoved();
460
461    assert((request->m_type == RubyRequestType_LD) ||
462           (request->m_type == RubyRequestType_IFETCH));
463
464    hitCallback(request, mach, data, true,
465                initialRequestTime, forwardRequestTime, firstResponseTime);
466}
467
468void
469Sequencer::hitCallback(SequencerRequest* srequest,
470                       GenericMachineType mach,
471                       DataBlock& data,
472                       bool success,
473                       Cycles initialRequestTime,
474                       Cycles forwardRequestTime,
475                       Cycles firstResponseTime)
476{
477    PacketPtr pkt = srequest->pkt;
478    Address request_address(pkt->getAddr());
479    Address request_line_address(pkt->getAddr());
480    request_line_address.makeLineAddress();
481    RubyRequestType type = srequest->m_type;
482    Cycles issued_time = srequest->issue_time;
483
484    // Set this cache entry to the most recently used
485    if (type == RubyRequestType_IFETCH) {
486        m_instCache_ptr->setMRU(request_line_address);
487    } else {
488        m_dataCache_ptr->setMRU(request_line_address);
489    }
490
491    assert(curCycle() >= issued_time);
492    Cycles miss_latency = curCycle() - issued_time;
493
494    // Profile the miss latency for all non-zero demand misses
495    if (miss_latency != 0) {
496        g_system_ptr->getProfiler()->missLatency(miss_latency, type, mach);
497
498        if (mach == GenericMachineType_L1Cache_wCC) {
499            g_system_ptr->getProfiler()->missLatencyWcc(issued_time,
500                initialRequestTime, forwardRequestTime,
501                firstResponseTime, curCycle());
502        }
503
504        if (mach == GenericMachineType_Directory) {
505            g_system_ptr->getProfiler()->missLatencyDir(issued_time,
506                initialRequestTime, forwardRequestTime,
507                firstResponseTime, curCycle());
508        }
509
510        DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %d cycles\n",
511                 curTick(), m_version, "Seq",
512                 success ? "Done" : "SC_Failed", "", "",
513                 request_address, miss_latency);
514    }
515
516    // update the data
517    if (g_system_ptr->m_warmup_enabled) {
518        assert(pkt->getPtr<uint8_t>(false) != NULL);
519        data.setData(pkt->getPtr<uint8_t>(false),
520                     request_address.getOffset(), pkt->getSize());
521    } else if (pkt->getPtr<uint8_t>(true) != NULL) {
522        if ((type == RubyRequestType_LD) ||
523            (type == RubyRequestType_IFETCH) ||
524            (type == RubyRequestType_RMW_Read) ||
525            (type == RubyRequestType_Locked_RMW_Read) ||
526            (type == RubyRequestType_Load_Linked)) {
527            memcpy(pkt->getPtr<uint8_t>(true),
528                   data.getData(request_address.getOffset(), pkt->getSize()),
529                   pkt->getSize());
530        } else {
531            data.setData(pkt->getPtr<uint8_t>(true),
532                         request_address.getOffset(), pkt->getSize());
533        }
534    } else {
535        DPRINTF(MemoryAccess,
536                "WARNING.  Data not transfered from Ruby to M5 for type %s\n",
537                RubyRequestType_to_string(type));
538    }
539
540    // If using the RubyTester, update the RubyTester sender state's
541    // subBlock with the recieved data.  The tester will later access
542    // this state.
543    // Note: RubyPort will access it's sender state before the
544    // RubyTester.
545    if (m_usingRubyTester) {
546        RubyPort::SenderState *reqSenderState =
547            safe_cast<RubyPort::SenderState*>(pkt->senderState);
548        // @todo This is a dangerous assumption on nothing else
549        // modifying the senderState
550        RubyTester::SenderState* testerSenderState =
551            safe_cast<RubyTester::SenderState*>(reqSenderState->predecessor);
552        testerSenderState->subBlock.mergeFrom(data);
553    }
554
555    delete srequest;
556
557    if (g_system_ptr->m_warmup_enabled) {
558        delete pkt;
559        g_system_ptr->m_cache_recorder->enqueueNextFetchRequest();
560    } else if (g_system_ptr->m_cooldown_enabled) {
561        delete pkt;
562        g_system_ptr->m_cache_recorder->enqueueNextFlushRequest();
563    } else {
564        ruby_hit_callback(pkt);
565    }
566}
567
568bool
569Sequencer::empty() const
570{
571    return m_writeRequestTable.empty() && m_readRequestTable.empty();
572}
573
574RequestStatus
575Sequencer::makeRequest(PacketPtr pkt)
576{
577    if (m_outstanding_count >= m_max_outstanding_requests) {
578        return RequestStatus_BufferFull;
579    }
580
581    RubyRequestType primary_type = RubyRequestType_NULL;
582    RubyRequestType secondary_type = RubyRequestType_NULL;
583
584    if (pkt->isLLSC()) {
585        //
586        // Alpha LL/SC instructions need to be handled carefully by the cache
587        // coherence protocol to ensure they follow the proper semantics. In
588        // particular, by identifying the operations as atomic, the protocol
589        // should understand that migratory sharing optimizations should not
590        // be performed (i.e. a load between the LL and SC should not steal
591        // away exclusive permission).
592        //
593        if (pkt->isWrite()) {
594            DPRINTF(RubySequencer, "Issuing SC\n");
595            primary_type = RubyRequestType_Store_Conditional;
596        } else {
597            DPRINTF(RubySequencer, "Issuing LL\n");
598            assert(pkt->isRead());
599            primary_type = RubyRequestType_Load_Linked;
600        }
601        secondary_type = RubyRequestType_ATOMIC;
602    } else if (pkt->req->isLocked()) {
603        //
604        // x86 locked instructions are translated to store cache coherence
605        // requests because these requests should always be treated as read
606        // exclusive operations and should leverage any migratory sharing
607        // optimization built into the protocol.
608        //
609        if (pkt->isWrite()) {
610            DPRINTF(RubySequencer, "Issuing Locked RMW Write\n");
611            primary_type = RubyRequestType_Locked_RMW_Write;
612        } else {
613            DPRINTF(RubySequencer, "Issuing Locked RMW Read\n");
614            assert(pkt->isRead());
615            primary_type = RubyRequestType_Locked_RMW_Read;
616        }
617        secondary_type = RubyRequestType_ST;
618    } else {
619        if (pkt->isRead()) {
620            if (pkt->req->isInstFetch()) {
621                primary_type = secondary_type = RubyRequestType_IFETCH;
622            } else {
623#if THE_ISA == X86_ISA
624                uint32_t flags = pkt->req->getFlags();
625                bool storeCheck = flags &
626                        (TheISA::StoreCheck << TheISA::FlagShift);
627#else
628                bool storeCheck = false;
629#endif // X86_ISA
630                if (storeCheck) {
631                    primary_type = RubyRequestType_RMW_Read;
632                    secondary_type = RubyRequestType_ST;
633                } else {
634                    primary_type = secondary_type = RubyRequestType_LD;
635                }
636            }
637        } else if (pkt->isWrite()) {
638            //
639            // Note: M5 packets do not differentiate ST from RMW_Write
640            //
641            primary_type = secondary_type = RubyRequestType_ST;
642        } else if (pkt->isFlush()) {
643          primary_type = secondary_type = RubyRequestType_FLUSH;
644        } else {
645            panic("Unsupported ruby packet type\n");
646        }
647    }
648
649    RequestStatus status = insertRequest(pkt, primary_type);
650    if (status != RequestStatus_Ready)
651        return status;
652
653    issueRequest(pkt, secondary_type);
654
655    // TODO: issue hardware prefetches here
656    return RequestStatus_Issued;
657}
658
659void
660Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type)
661{
662    assert(pkt != NULL);
663    int proc_id = -1;
664    if (pkt->req->hasContextId()) {
665        proc_id = pkt->req->contextId();
666    }
667
668    // If valid, copy the pc to the ruby request
669    Addr pc = 0;
670    if (pkt->req->hasPC()) {
671        pc = pkt->req->getPC();
672    }
673
674    RubyRequest *msg = new RubyRequest(clockEdge(), pkt->getAddr(),
675                                       pkt->getPtr<uint8_t>(true),
676                                       pkt->getSize(), pc, secondary_type,
677                                       RubyAccessMode_Supervisor, pkt,
678                                       PrefetchBit_No, proc_id);
679
680    DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %s\n",
681            curTick(), m_version, "Seq", "Begin", "", "",
682            msg->getPhysicalAddress(),
683            RubyRequestType_to_string(secondary_type));
684
685    Cycles latency(0);  // initialzed to an null value
686
687    if (secondary_type == RubyRequestType_IFETCH)
688        latency = m_instCache_ptr->getLatency();
689    else
690        latency = m_dataCache_ptr->getLatency();
691
692    // Send the message to the cache controller
693    assert(latency > 0);
694
695    assert(m_mandatory_q_ptr != NULL);
696    m_mandatory_q_ptr->enqueue(msg, latency);
697}
698
699template <class KEY, class VALUE>
700std::ostream &
701operator<<(ostream &out, const m5::hash_map<KEY, VALUE> &map)
702{
703    typename m5::hash_map<KEY, VALUE>::const_iterator i = map.begin();
704    typename m5::hash_map<KEY, VALUE>::const_iterator end = map.end();
705
706    out << "[";
707    for (; i != end; ++i)
708        out << " " << i->first << "=" << i->second;
709    out << " ]";
710
711    return out;
712}
713
714void
715Sequencer::print(ostream& out) const
716{
717    out << "[Sequencer: " << m_version
718        << ", outstanding requests: " << m_outstanding_count
719        << ", read request table: " << m_readRequestTable
720        << ", write request table: " << m_writeRequestTable
721        << "]";
722}
723
724// this can be called from setState whenever coherence permissions are
725// upgraded when invoked, coherence violations will be checked for the
726// given block
727void
728Sequencer::checkCoherence(const Address& addr)
729{
730#ifdef CHECK_COHERENCE
731    g_system_ptr->checkGlobalCoherenceInvariant(addr);
732#endif
733}
734
735void
736Sequencer::recordRequestType(SequencerRequestType requestType) {
737    DPRINTF(RubyStats, "Recorded statistic: %s\n",
738            SequencerRequestType_to_string(requestType));
739}
740
741
742void
743Sequencer::evictionCallback(const Address& address)
744{
745    ruby_eviction_callback(address);
746}
747