Sequencer.cc revision 9342:6fec8f26e56d 
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "base/misc.hh"
30#include "base/str.hh"
31#include "config/the_isa.hh"
32#if THE_ISA == X86_ISA
33#include "arch/x86/insts/microldstop.hh"
34#endif // X86_ISA
35#include "cpu/testers/rubytest/RubyTester.hh"
36#include "debug/MemoryAccess.hh"
37#include "debug/ProtocolTrace.hh"
38#include "debug/RubySequencer.hh"
39#include "debug/RubyStats.hh"
40#include "mem/protocol/PrefetchBit.hh"
41#include "mem/protocol/RubyAccessMode.hh"
42#include "mem/ruby/buffers/MessageBuffer.hh"
43#include "mem/ruby/common/Global.hh"
44#include "mem/ruby/profiler/Profiler.hh"
45#include "mem/ruby/slicc_interface/RubyRequest.hh"
46#include "mem/ruby/system/Sequencer.hh"
47#include "mem/ruby/system/System.hh"
48#include "mem/packet.hh"
49
50using namespace std;
51
52Sequencer *
53RubySequencerParams::create()
54{
55    return new Sequencer(this);
56}
57
58Sequencer::Sequencer(const Params *p)
59    : RubyPort(p), deadlockCheckEvent(this)
60{
61    m_store_waiting_on_load_cycles = 0;
62    m_store_waiting_on_store_cycles = 0;
63    m_load_waiting_on_store_cycles = 0;
64    m_load_waiting_on_load_cycles = 0;
65
66    m_outstanding_count = 0;
67
68    m_instCache_ptr = p->icache;
69    m_dataCache_ptr = p->dcache;
70    m_max_outstanding_requests = p->max_outstanding_requests;
71    m_deadlock_threshold = p->deadlock_threshold;
72
73    assert(m_max_outstanding_requests > 0);
74    assert(m_deadlock_threshold > 0);
75    assert(m_instCache_ptr != NULL);
76    assert(m_dataCache_ptr != NULL);
77
78    m_usingNetworkTester = p->using_network_tester;
79}
80
81Sequencer::~Sequencer()
82{
83}
84
85void
86Sequencer::wakeup()
87{
88    assert(getDrainState() != Drainable::Draining);
89
90    // Check for deadlock of any of the requests
91    Time current_time = g_system_ptr->getTime();
92
93    // Check across all outstanding requests
94    int total_outstanding = 0;
95
96    RequestTable::iterator read = m_readRequestTable.begin();
97    RequestTable::iterator read_end = m_readRequestTable.end();
98    for (; read != read_end; ++read) {
99        SequencerRequest* request = read->second;
100        if (current_time - request->issue_time < m_deadlock_threshold)
101            continue;
102
103        panic("Possible Deadlock detected. Aborting!\n"
104             "version: %d request.paddr: 0x%x m_readRequestTable: %d "
105             "current time: %u issue_time: %d difference: %d\n", m_version,
106             Address(request->pkt->getAddr()), m_readRequestTable.size(),
107             current_time, request->issue_time,
108             current_time - request->issue_time);
109    }
110
111    RequestTable::iterator write = m_writeRequestTable.begin();
112    RequestTable::iterator write_end = m_writeRequestTable.end();
113    for (; write != write_end; ++write) {
114        SequencerRequest* request = write->second;
115        if (current_time - request->issue_time < m_deadlock_threshold)
116            continue;
117
118        panic("Possible Deadlock detected. Aborting!\n"
119             "version: %d request.paddr: 0x%x m_writeRequestTable: %d "
120             "current time: %u issue_time: %d difference: %d\n", m_version,
121             Address(request->pkt->getAddr()), m_writeRequestTable.size(),
122             current_time, request->issue_time,
123             current_time - request->issue_time);
124    }
125
126    total_outstanding += m_writeRequestTable.size();
127    total_outstanding += m_readRequestTable.size();
128
129    assert(m_outstanding_count == total_outstanding);
130
131    if (m_outstanding_count > 0) {
132        // If there are still outstanding requests, keep checking
133        schedule(deadlockCheckEvent,
134            g_system_ptr->clockPeriod() * m_deadlock_threshold + curTick());
135    }
136}
137
138void
139Sequencer::printStats(ostream & out) const
140{
141    out << "Sequencer: " << m_name << endl
142        << "  store_waiting_on_load_cycles: "
143        << m_store_waiting_on_load_cycles << endl
144        << "  store_waiting_on_store_cycles: "
145        << m_store_waiting_on_store_cycles << endl
146        << "  load_waiting_on_load_cycles: "
147        << m_load_waiting_on_load_cycles << endl
148        << "  load_waiting_on_store_cycles: "
149        << m_load_waiting_on_store_cycles << endl;
150}
151
152void
153Sequencer::printProgress(ostream& out) const
154{
155#if 0
156    int total_demand = 0;
157    out << "Sequencer Stats Version " << m_version << endl;
158    out << "Current time = " << g_system_ptr->getTime() << endl;
159    out << "---------------" << endl;
160    out << "outstanding requests" << endl;
161
162    out << "proc " << m_Read
163        << " version Requests = " << m_readRequestTable.size() << endl;
164
165    // print the request table
166    RequestTable::iterator read = m_readRequestTable.begin();
167    RequestTable::iterator read_end = m_readRequestTable.end();
168    for (; read != read_end; ++read) {
169        SequencerRequest* request = read->second;
170        out << "\tRequest[ " << i << " ] = " << request->type
171            << " Address " << rkeys[i]
172            << " Posted " << request->issue_time
173            << " PF " << PrefetchBit_No << endl;
174        total_demand++;
175    }
176
177    out << "proc " << m_version
178        << " Write Requests = " << m_writeRequestTable.size << endl;
179
180    // print the request table
181    RequestTable::iterator write = m_writeRequestTable.begin();
182    RequestTable::iterator write_end = m_writeRequestTable.end();
183    for (; write != write_end; ++write) {
184        SequencerRequest* request = write->second;
185        out << "\tRequest[ " << i << " ] = " << request.getType()
186            << " Address " << wkeys[i]
187            << " Posted " << request.getTime()
188            << " PF " << request.getPrefetch() << endl;
189        if (request.getPrefetch() == PrefetchBit_No) {
190            total_demand++;
191        }
192    }
193
194    out << endl;
195
196    out << "Total Number Outstanding: " << m_outstanding_count << endl
197        << "Total Number Demand     : " << total_demand << endl
198        << "Total Number Prefetches : " << m_outstanding_count - total_demand
199        << endl << endl << endl;
200#endif
201}
202
203// Insert the request on the correct request table.  Return true if
204// the entry was already present.
205RequestStatus
206Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
207{
208    assert(m_outstanding_count ==
209        (m_writeRequestTable.size() + m_readRequestTable.size()));
210
211    // See if we should schedule a deadlock check
212    if (!deadlockCheckEvent.scheduled() &&
213        getDrainState() != Drainable::Draining) {
214        schedule(deadlockCheckEvent,
215            g_system_ptr->clockPeriod() * m_deadlock_threshold + curTick());
216    }
217
218    Address line_addr(pkt->getAddr());
219    line_addr.makeLineAddress();
220    // Create a default entry, mapping the address to NULL, the cast is
221    // there to make gcc 4.4 happy
222    RequestTable::value_type default_entry(line_addr,
223                                           (SequencerRequest*) NULL);
224
225    if ((request_type == RubyRequestType_ST) ||
226        (request_type == RubyRequestType_RMW_Read) ||
227        (request_type == RubyRequestType_RMW_Write) ||
228        (request_type == RubyRequestType_Load_Linked) ||
229        (request_type == RubyRequestType_Store_Conditional) ||
230        (request_type == RubyRequestType_Locked_RMW_Read) ||
231        (request_type == RubyRequestType_Locked_RMW_Write) ||
232        (request_type == RubyRequestType_FLUSH)) {
233
234        // Check if there is any outstanding read request for the same
235        // cache line.
236        if (m_readRequestTable.count(line_addr) > 0) {
237            m_store_waiting_on_load_cycles++;
238            return RequestStatus_Aliased;
239        }
240
241        pair<RequestTable::iterator, bool> r =
242            m_writeRequestTable.insert(default_entry);
243        if (r.second) {
244            RequestTable::iterator i = r.first;
245            i->second = new SequencerRequest(pkt, request_type,
246                                             g_system_ptr->getTime());
247            m_outstanding_count++;
248        } else {
249          // There is an outstanding write request for the cache line
250          m_store_waiting_on_store_cycles++;
251          return RequestStatus_Aliased;
252        }
253    } else {
254        // Check if there is any outstanding write request for the same
255        // cache line.
256        if (m_writeRequestTable.count(line_addr) > 0) {
257            m_load_waiting_on_store_cycles++;
258            return RequestStatus_Aliased;
259        }
260
261        pair<RequestTable::iterator, bool> r =
262            m_readRequestTable.insert(default_entry);
263
264        if (r.second) {
265            RequestTable::iterator i = r.first;
266            i->second = new SequencerRequest(pkt, request_type,
267                                             g_system_ptr->getTime());
268            m_outstanding_count++;
269        } else {
270            // There is an outstanding read request for the cache line
271            m_load_waiting_on_load_cycles++;
272            return RequestStatus_Aliased;
273        }
274    }
275
276    g_system_ptr->getProfiler()->sequencerRequests(m_outstanding_count);
277    assert(m_outstanding_count ==
278        (m_writeRequestTable.size() + m_readRequestTable.size()));
279
280    return RequestStatus_Ready;
281}
282
283void
284Sequencer::markRemoved()
285{
286    m_outstanding_count--;
287    assert(m_outstanding_count ==
288           m_writeRequestTable.size() + m_readRequestTable.size());
289}
290
291void
292Sequencer::removeRequest(SequencerRequest* srequest)
293{
294    assert(m_outstanding_count ==
295           m_writeRequestTable.size() + m_readRequestTable.size());
296
297    Address line_addr(srequest->pkt->getAddr());
298    line_addr.makeLineAddress();
299    if ((srequest->m_type == RubyRequestType_ST) ||
300        (srequest->m_type == RubyRequestType_RMW_Read) ||
301        (srequest->m_type == RubyRequestType_RMW_Write) ||
302        (srequest->m_type == RubyRequestType_Load_Linked) ||
303        (srequest->m_type == RubyRequestType_Store_Conditional) ||
304        (srequest->m_type == RubyRequestType_Locked_RMW_Read) ||
305        (srequest->m_type == RubyRequestType_Locked_RMW_Write)) {
306        m_writeRequestTable.erase(line_addr);
307    } else {
308        m_readRequestTable.erase(line_addr);
309    }
310
311    markRemoved();
312}
313
314bool
315Sequencer::handleLlsc(const Address& address, SequencerRequest* request)
316{
317    //
318    // The success flag indicates whether the LLSC operation was successful.
319    // LL ops will always succeed, but SC may fail if the cache line is no
320    // longer locked.
321    //
322    bool success = true;
323    if (request->m_type == RubyRequestType_Store_Conditional) {
324        if (!m_dataCache_ptr->isLocked(address, m_version)) {
325            //
326            // For failed SC requests, indicate the failure to the cpu by
327            // setting the extra data to zero.
328            //
329            request->pkt->req->setExtraData(0);
330            success = false;
331        } else {
332            //
333            // For successful SC requests, indicate the success to the cpu by
334            // setting the extra data to one.
335            //
336            request->pkt->req->setExtraData(1);
337        }
338        //
339        // Independent of success, all SC operations must clear the lock
340        //
341        m_dataCache_ptr->clearLocked(address);
342    } else if (request->m_type == RubyRequestType_Load_Linked) {
343        //
344        // Note: To fully follow Alpha LLSC semantics, should the LL clear any
345        // previously locked cache lines?
346        //
347        m_dataCache_ptr->setLocked(address, m_version);
348    } else if ((m_dataCache_ptr->isTagPresent(address)) &&
349               (m_dataCache_ptr->isLocked(address, m_version))) {
350        //
351        // Normal writes should clear the locked address
352        //
353        m_dataCache_ptr->clearLocked(address);
354    }
355    return success;
356}
357
358void
359Sequencer::writeCallback(const Address& address, DataBlock& data)
360{
361    writeCallback(address, GenericMachineType_NULL, data);
362}
363
364void
365Sequencer::writeCallback(const Address& address,
366                         GenericMachineType mach,
367                         DataBlock& data)
368{
369    writeCallback(address, mach, data, 0, 0, 0);
370}
371
372void
373Sequencer::writeCallback(const Address& address,
374                         GenericMachineType mach,
375                         DataBlock& data,
376                         Time initialRequestTime,
377                         Time forwardRequestTime,
378                         Time firstResponseTime)
379{
380    assert(address == line_address(address));
381    assert(m_writeRequestTable.count(line_address(address)));
382
383    RequestTable::iterator i = m_writeRequestTable.find(address);
384    assert(i != m_writeRequestTable.end());
385    SequencerRequest* request = i->second;
386
387    m_writeRequestTable.erase(i);
388    markRemoved();
389
390    assert((request->m_type == RubyRequestType_ST) ||
391           (request->m_type == RubyRequestType_ATOMIC) ||
392           (request->m_type == RubyRequestType_RMW_Read) ||
393           (request->m_type == RubyRequestType_RMW_Write) ||
394           (request->m_type == RubyRequestType_Load_Linked) ||
395           (request->m_type == RubyRequestType_Store_Conditional) ||
396           (request->m_type == RubyRequestType_Locked_RMW_Read) ||
397           (request->m_type == RubyRequestType_Locked_RMW_Write) ||
398           (request->m_type == RubyRequestType_FLUSH));
399
400
401    //
402    // For Alpha, properly handle LL, SC, and write requests with respect to
403    // locked cache blocks.
404    //
405    // Not valid for Network_test protocl
406    //
407    bool success = true;
408    if(!m_usingNetworkTester)
409        success = handleLlsc(address, request);
410
411    if (request->m_type == RubyRequestType_Locked_RMW_Read) {
412        m_controller->blockOnQueue(address, m_mandatory_q_ptr);
413    } else if (request->m_type == RubyRequestType_Locked_RMW_Write) {
414        m_controller->unblock(address);
415    }
416
417    hitCallback(request, mach, data, success,
418                initialRequestTime, forwardRequestTime, firstResponseTime);
419}
420
421void
422Sequencer::readCallback(const Address& address, DataBlock& data)
423{
424    readCallback(address, GenericMachineType_NULL, data);
425}
426
427void
428Sequencer::readCallback(const Address& address,
429                        GenericMachineType mach,
430                        DataBlock& data)
431{
432    readCallback(address, mach, data, 0, 0, 0);
433}
434
435void
436Sequencer::readCallback(const Address& address,
437                        GenericMachineType mach,
438                        DataBlock& data,
439                        Time initialRequestTime,
440                        Time forwardRequestTime,
441                        Time firstResponseTime)
442{
443    assert(address == line_address(address));
444    assert(m_readRequestTable.count(line_address(address)));
445
446    RequestTable::iterator i = m_readRequestTable.find(address);
447    assert(i != m_readRequestTable.end());
448    SequencerRequest* request = i->second;
449
450    m_readRequestTable.erase(i);
451    markRemoved();
452
453    assert((request->m_type == RubyRequestType_LD) ||
454           (request->m_type == RubyRequestType_IFETCH));
455
456    hitCallback(request, mach, data, true,
457                initialRequestTime, forwardRequestTime, firstResponseTime);
458}
459
460void
461Sequencer::hitCallback(SequencerRequest* srequest,
462                       GenericMachineType mach,
463                       DataBlock& data,
464                       bool success,
465                       Time initialRequestTime,
466                       Time forwardRequestTime,
467                       Time firstResponseTime)
468{
469    PacketPtr pkt = srequest->pkt;
470    Address request_address(pkt->getAddr());
471    Address request_line_address(pkt->getAddr());
472    request_line_address.makeLineAddress();
473    RubyRequestType type = srequest->m_type;
474    Time issued_time = srequest->issue_time;
475
476    // Set this cache entry to the most recently used
477    if (type == RubyRequestType_IFETCH) {
478        m_instCache_ptr->setMRU(request_line_address);
479    } else {
480        m_dataCache_ptr->setMRU(request_line_address);
481    }
482
483    assert(g_system_ptr->getTime() >= issued_time);
484    Time miss_latency = g_system_ptr->getTime() - issued_time;
485
486    // Profile the miss latency for all non-zero demand misses
487    if (miss_latency != 0) {
488        g_system_ptr->getProfiler()->missLatency(miss_latency, type, mach);
489
490        if (mach == GenericMachineType_L1Cache_wCC) {
491            g_system_ptr->getProfiler()->missLatencyWcc(issued_time,
492                                                   initialRequestTime,
493                                                   forwardRequestTime,
494                                                   firstResponseTime,
495                                                   g_system_ptr->getTime());
496        }
497
498        if (mach == GenericMachineType_Directory) {
499            g_system_ptr->getProfiler()->missLatencyDir(issued_time,
500                                                   initialRequestTime,
501                                                   forwardRequestTime,
502                                                   firstResponseTime,
503                                                   g_system_ptr->getTime());
504        }
505
506        DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %d cycles\n",
507                 curTick(), m_version, "Seq",
508                 success ? "Done" : "SC_Failed", "", "",
509                 request_address, miss_latency);
510    }
511
512    // update the data
513    if (g_system_ptr->m_warmup_enabled) {
514        assert(pkt->getPtr<uint8_t>(false) != NULL);
515        data.setData(pkt->getPtr<uint8_t>(false),
516                     request_address.getOffset(), pkt->getSize());
517    } else if (pkt->getPtr<uint8_t>(true) != NULL) {
518        if ((type == RubyRequestType_LD) ||
519            (type == RubyRequestType_IFETCH) ||
520            (type == RubyRequestType_RMW_Read) ||
521            (type == RubyRequestType_Locked_RMW_Read) ||
522            (type == RubyRequestType_Load_Linked)) {
523            memcpy(pkt->getPtr<uint8_t>(true),
524                   data.getData(request_address.getOffset(), pkt->getSize()),
525                   pkt->getSize());
526        } else {
527            data.setData(pkt->getPtr<uint8_t>(true),
528                         request_address.getOffset(), pkt->getSize());
529        }
530    } else {
531        DPRINTF(MemoryAccess,
532                "WARNING.  Data not transfered from Ruby to M5 for type %s\n",
533                RubyRequestType_to_string(type));
534    }
535
536    // If using the RubyTester, update the RubyTester sender state's
537    // subBlock with the recieved data.  The tester will later access
538    // this state.
539    // Note: RubyPort will access it's sender state before the
540    // RubyTester.
541    if (m_usingRubyTester) {
542        RubyPort::SenderState *requestSenderState =
543            safe_cast<RubyPort::SenderState*>(pkt->senderState);
544        RubyTester::SenderState* testerSenderState =
545            safe_cast<RubyTester::SenderState*>(requestSenderState->saved);
546        testerSenderState->subBlock->mergeFrom(data);
547    }
548
549    delete srequest;
550
551    if (g_system_ptr->m_warmup_enabled) {
552        delete pkt;
553        g_system_ptr->m_cache_recorder->enqueueNextFetchRequest();
554    } else if (g_system_ptr->m_cooldown_enabled) {
555        delete pkt;
556        g_system_ptr->m_cache_recorder->enqueueNextFlushRequest();
557    } else {
558        ruby_hit_callback(pkt);
559    }
560}
561
562bool
563Sequencer::empty() const
564{
565    return m_writeRequestTable.empty() && m_readRequestTable.empty();
566}
567
568RequestStatus
569Sequencer::makeRequest(PacketPtr pkt)
570{
571    if (m_outstanding_count >= m_max_outstanding_requests) {
572        return RequestStatus_BufferFull;
573    }
574
575    RubyRequestType primary_type = RubyRequestType_NULL;
576    RubyRequestType secondary_type = RubyRequestType_NULL;
577
578    if (pkt->isLLSC()) {
579        //
580        // Alpha LL/SC instructions need to be handled carefully by the cache
581        // coherence protocol to ensure they follow the proper semantics. In
582        // particular, by identifying the operations as atomic, the protocol
583        // should understand that migratory sharing optimizations should not
584        // be performed (i.e. a load between the LL and SC should not steal
585        // away exclusive permission).
586        //
587        if (pkt->isWrite()) {
588            DPRINTF(RubySequencer, "Issuing SC\n");
589            primary_type = RubyRequestType_Store_Conditional;
590        } else {
591            DPRINTF(RubySequencer, "Issuing LL\n");
592            assert(pkt->isRead());
593            primary_type = RubyRequestType_Load_Linked;
594        }
595        secondary_type = RubyRequestType_ATOMIC;
596    } else if (pkt->req->isLocked()) {
597        //
598        // x86 locked instructions are translated to store cache coherence
599        // requests because these requests should always be treated as read
600        // exclusive operations and should leverage any migratory sharing
601        // optimization built into the protocol.
602        //
603        if (pkt->isWrite()) {
604            DPRINTF(RubySequencer, "Issuing Locked RMW Write\n");
605            primary_type = RubyRequestType_Locked_RMW_Write;
606        } else {
607            DPRINTF(RubySequencer, "Issuing Locked RMW Read\n");
608            assert(pkt->isRead());
609            primary_type = RubyRequestType_Locked_RMW_Read;
610        }
611        secondary_type = RubyRequestType_ST;
612    } else {
613        if (pkt->isRead()) {
614            if (pkt->req->isInstFetch()) {
615                primary_type = secondary_type = RubyRequestType_IFETCH;
616            } else {
617#if THE_ISA == X86_ISA
618                uint32_t flags = pkt->req->getFlags();
619                bool storeCheck = flags &
620                        (TheISA::StoreCheck << TheISA::FlagShift);
621#else
622                bool storeCheck = false;
623#endif // X86_ISA
624                if (storeCheck) {
625                    primary_type = RubyRequestType_RMW_Read;
626                    secondary_type = RubyRequestType_ST;
627                } else {
628                    primary_type = secondary_type = RubyRequestType_LD;
629                }
630            }
631        } else if (pkt->isWrite()) {
632            //
633            // Note: M5 packets do not differentiate ST from RMW_Write
634            //
635            primary_type = secondary_type = RubyRequestType_ST;
636        } else if (pkt->isFlush()) {
637          primary_type = secondary_type = RubyRequestType_FLUSH;
638        } else {
639            panic("Unsupported ruby packet type\n");
640        }
641    }
642
643    RequestStatus status = insertRequest(pkt, primary_type);
644    if (status != RequestStatus_Ready)
645        return status;
646
647    issueRequest(pkt, secondary_type);
648
649    // TODO: issue hardware prefetches here
650    return RequestStatus_Issued;
651}
652
653void
654Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type)
655{
656    assert(pkt != NULL);
657    int proc_id = -1;
658    if (pkt->req->hasContextId()) {
659        proc_id = pkt->req->contextId();
660    }
661
662    // If valid, copy the pc to the ruby request
663    Addr pc = 0;
664    if (pkt->req->hasPC()) {
665        pc = pkt->req->getPC();
666    }
667
668    RubyRequest *msg = new RubyRequest(pkt->getAddr(),
669                                       pkt->getPtr<uint8_t>(true),
670                                       pkt->getSize(), pc, secondary_type,
671                                       RubyAccessMode_Supervisor, pkt,
672                                       PrefetchBit_No, proc_id);
673
674    DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %s\n",
675            curTick(), m_version, "Seq", "Begin", "", "",
676            msg->getPhysicalAddress(),
677            RubyRequestType_to_string(secondary_type));
678
679    Time latency = 0;  // initialzed to an null value
680
681    if (secondary_type == RubyRequestType_IFETCH)
682        latency = m_instCache_ptr->getLatency();
683    else
684        latency = m_dataCache_ptr->getLatency();
685
686    // Send the message to the cache controller
687    assert(latency > 0);
688
689    assert(m_mandatory_q_ptr != NULL);
690    m_mandatory_q_ptr->enqueue(msg, latency);
691}
692
693template <class KEY, class VALUE>
694std::ostream &
695operator<<(ostream &out, const m5::hash_map<KEY, VALUE> &map)
696{
697    typename m5::hash_map<KEY, VALUE>::const_iterator i = map.begin();
698    typename m5::hash_map<KEY, VALUE>::const_iterator end = map.end();
699
700    out << "[";
701    for (; i != end; ++i)
702        out << " " << i->first << "=" << i->second;
703    out << " ]";
704
705    return out;
706}
707
708void
709Sequencer::print(ostream& out) const
710{
711    out << "[Sequencer: " << m_version
712        << ", outstanding requests: " << m_outstanding_count
713        << ", read request table: " << m_readRequestTable
714        << ", write request table: " << m_writeRequestTable
715        << "]";
716}
717
718// this can be called from setState whenever coherence permissions are
719// upgraded when invoked, coherence violations will be checked for the
720// given block
721void
722Sequencer::checkCoherence(const Address& addr)
723{
724#ifdef CHECK_COHERENCE
725    g_system_ptr->checkGlobalCoherenceInvariant(addr);
726#endif
727}
728
729void
730Sequencer::recordRequestType(SequencerRequestType requestType) {
731    DPRINTF(RubyStats, "Recorded statistic: %s\n",
732            SequencerRequestType_to_string(requestType));
733}
734
735
736void
737Sequencer::evictionCallback(const Address& address)
738{
739    ruby_eviction_callback(address);
740}
741