Sequencer.cc revision 9216:a5f937d152bf 
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "base/misc.hh"
30#include "base/str.hh"
31#include "config/the_isa.hh"
32#if THE_ISA == X86_ISA
33#include "arch/x86/insts/microldstop.hh"
34#endif // X86_ISA
35#include "cpu/testers/rubytest/RubyTester.hh"
36#include "debug/MemoryAccess.hh"
37#include "debug/ProtocolTrace.hh"
38#include "debug/RubySequencer.hh"
39#include "debug/RubyStats.hh"
40#include "mem/protocol/PrefetchBit.hh"
41#include "mem/protocol/RubyAccessMode.hh"
42#include "mem/ruby/buffers/MessageBuffer.hh"
43#include "mem/ruby/common/Global.hh"
44#include "mem/ruby/profiler/Profiler.hh"
45#include "mem/ruby/slicc_interface/RubyRequest.hh"
46#include "mem/ruby/system/Sequencer.hh"
47#include "mem/ruby/system/System.hh"
48#include "mem/packet.hh"
49
50using namespace std;
51
52Sequencer *
53RubySequencerParams::create()
54{
55    return new Sequencer(this);
56}
57
58Sequencer::Sequencer(const Params *p)
59    : RubyPort(p), deadlockCheckEvent(this)
60{
61    m_store_waiting_on_load_cycles = 0;
62    m_store_waiting_on_store_cycles = 0;
63    m_load_waiting_on_store_cycles = 0;
64    m_load_waiting_on_load_cycles = 0;
65
66    m_outstanding_count = 0;
67
68    m_instCache_ptr = p->icache;
69    m_dataCache_ptr = p->dcache;
70    m_max_outstanding_requests = p->max_outstanding_requests;
71    m_deadlock_threshold = p->deadlock_threshold;
72
73    assert(m_max_outstanding_requests > 0);
74    assert(m_deadlock_threshold > 0);
75    assert(m_instCache_ptr != NULL);
76    assert(m_dataCache_ptr != NULL);
77
78    m_usingNetworkTester = p->using_network_tester;
79}
80
81Sequencer::~Sequencer()
82{
83}
84
85void
86Sequencer::wakeup()
87{
88    // Check for deadlock of any of the requests
89    Time current_time = g_system_ptr->getTime();
90
91    // Check across all outstanding requests
92    int total_outstanding = 0;
93
94    RequestTable::iterator read = m_readRequestTable.begin();
95    RequestTable::iterator read_end = m_readRequestTable.end();
96    for (; read != read_end; ++read) {
97        SequencerRequest* request = read->second;
98        if (current_time - request->issue_time < m_deadlock_threshold)
99            continue;
100
101        panic("Possible Deadlock detected. Aborting!\n"
102             "version: %d request.paddr: 0x%x m_readRequestTable: %d "
103             "current time: %u issue_time: %d difference: %d\n", m_version,
104             Address(request->pkt->getAddr()), m_readRequestTable.size(),
105             current_time, request->issue_time,
106             current_time - request->issue_time);
107    }
108
109    RequestTable::iterator write = m_writeRequestTable.begin();
110    RequestTable::iterator write_end = m_writeRequestTable.end();
111    for (; write != write_end; ++write) {
112        SequencerRequest* request = write->second;
113        if (current_time - request->issue_time < m_deadlock_threshold)
114            continue;
115
116        panic("Possible Deadlock detected. Aborting!\n"
117             "version: %d request.paddr: 0x%x m_writeRequestTable: %d "
118             "current time: %u issue_time: %d difference: %d\n", m_version,
119             Address(request->pkt->getAddr()), m_writeRequestTable.size(),
120             current_time, request->issue_time,
121             current_time - request->issue_time);
122    }
123
124    total_outstanding += m_writeRequestTable.size();
125    total_outstanding += m_readRequestTable.size();
126
127    assert(m_outstanding_count == total_outstanding);
128
129    if (m_outstanding_count > 0) {
130        // If there are still outstanding requests, keep checking
131        schedule(deadlockCheckEvent,
132            g_system_ptr->clockPeriod() * m_deadlock_threshold + curTick());
133    }
134}
135
136void
137Sequencer::printStats(ostream & out) const
138{
139    out << "Sequencer: " << m_name << endl
140        << "  store_waiting_on_load_cycles: "
141        << m_store_waiting_on_load_cycles << endl
142        << "  store_waiting_on_store_cycles: "
143        << m_store_waiting_on_store_cycles << endl
144        << "  load_waiting_on_load_cycles: "
145        << m_load_waiting_on_load_cycles << endl
146        << "  load_waiting_on_store_cycles: "
147        << m_load_waiting_on_store_cycles << endl;
148}
149
150void
151Sequencer::printProgress(ostream& out) const
152{
153#if 0
154    int total_demand = 0;
155    out << "Sequencer Stats Version " << m_version << endl;
156    out << "Current time = " << g_system_ptr->getTime() << endl;
157    out << "---------------" << endl;
158    out << "outstanding requests" << endl;
159
160    out << "proc " << m_Read
161        << " version Requests = " << m_readRequestTable.size() << endl;
162
163    // print the request table
164    RequestTable::iterator read = m_readRequestTable.begin();
165    RequestTable::iterator read_end = m_readRequestTable.end();
166    for (; read != read_end; ++read) {
167        SequencerRequest* request = read->second;
168        out << "\tRequest[ " << i << " ] = " << request->type
169            << " Address " << rkeys[i]
170            << " Posted " << request->issue_time
171            << " PF " << PrefetchBit_No << endl;
172        total_demand++;
173    }
174
175    out << "proc " << m_version
176        << " Write Requests = " << m_writeRequestTable.size << endl;
177
178    // print the request table
179    RequestTable::iterator write = m_writeRequestTable.begin();
180    RequestTable::iterator write_end = m_writeRequestTable.end();
181    for (; write != write_end; ++write) {
182        SequencerRequest* request = write->second;
183        out << "\tRequest[ " << i << " ] = " << request.getType()
184            << " Address " << wkeys[i]
185            << " Posted " << request.getTime()
186            << " PF " << request.getPrefetch() << endl;
187        if (request.getPrefetch() == PrefetchBit_No) {
188            total_demand++;
189        }
190    }
191
192    out << endl;
193
194    out << "Total Number Outstanding: " << m_outstanding_count << endl
195        << "Total Number Demand     : " << total_demand << endl
196        << "Total Number Prefetches : " << m_outstanding_count - total_demand
197        << endl << endl << endl;
198#endif
199}
200
201// Insert the request on the correct request table.  Return true if
202// the entry was already present.
203RequestStatus
204Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
205{
206    assert(m_outstanding_count ==
207        (m_writeRequestTable.size() + m_readRequestTable.size()));
208
209    // See if we should schedule a deadlock check
210    if (deadlockCheckEvent.scheduled() == false) {
211        schedule(deadlockCheckEvent,
212            g_system_ptr->clockPeriod() * m_deadlock_threshold + curTick());
213    }
214
215    Address line_addr(pkt->getAddr());
216    line_addr.makeLineAddress();
217    if ((request_type == RubyRequestType_ST) ||
218        (request_type == RubyRequestType_RMW_Read) ||
219        (request_type == RubyRequestType_RMW_Write) ||
220        (request_type == RubyRequestType_Load_Linked) ||
221        (request_type == RubyRequestType_Store_Conditional) ||
222        (request_type == RubyRequestType_Locked_RMW_Read) ||
223        (request_type == RubyRequestType_Locked_RMW_Write) ||
224        (request_type == RubyRequestType_FLUSH)) {
225
226        // Check if there is any outstanding read request for the same
227        // cache line.
228        if (m_readRequestTable.count(line_addr) > 0) {
229            m_store_waiting_on_load_cycles++;
230            return RequestStatus_Aliased;
231        }
232
233        pair<RequestTable::iterator, bool> r =
234            m_writeRequestTable.insert(RequestTable::value_type(line_addr, 0));
235        if (r.second) {
236            RequestTable::iterator i = r.first;
237            i->second = new SequencerRequest(pkt, request_type,
238                                             g_system_ptr->getTime());
239            m_outstanding_count++;
240        } else {
241          // There is an outstanding write request for the cache line
242          m_store_waiting_on_store_cycles++;
243          return RequestStatus_Aliased;
244        }
245    } else {
246        // Check if there is any outstanding write request for the same
247        // cache line.
248        if (m_writeRequestTable.count(line_addr) > 0) {
249            m_load_waiting_on_store_cycles++;
250            return RequestStatus_Aliased;
251        }
252
253        pair<RequestTable::iterator, bool> r =
254            m_readRequestTable.insert(RequestTable::value_type(line_addr, 0));
255
256        if (r.second) {
257            RequestTable::iterator i = r.first;
258            i->second = new SequencerRequest(pkt, request_type,
259                                             g_system_ptr->getTime());
260            m_outstanding_count++;
261        } else {
262            // There is an outstanding read request for the cache line
263            m_load_waiting_on_load_cycles++;
264            return RequestStatus_Aliased;
265        }
266    }
267
268    g_system_ptr->getProfiler()->sequencerRequests(m_outstanding_count);
269    assert(m_outstanding_count ==
270        (m_writeRequestTable.size() + m_readRequestTable.size()));
271
272    return RequestStatus_Ready;
273}
274
275void
276Sequencer::markRemoved()
277{
278    m_outstanding_count--;
279    assert(m_outstanding_count ==
280           m_writeRequestTable.size() + m_readRequestTable.size());
281}
282
283void
284Sequencer::removeRequest(SequencerRequest* srequest)
285{
286    assert(m_outstanding_count ==
287           m_writeRequestTable.size() + m_readRequestTable.size());
288
289    Address line_addr(srequest->pkt->getAddr());
290    line_addr.makeLineAddress();
291    if ((srequest->m_type == RubyRequestType_ST) ||
292        (srequest->m_type == RubyRequestType_RMW_Read) ||
293        (srequest->m_type == RubyRequestType_RMW_Write) ||
294        (srequest->m_type == RubyRequestType_Load_Linked) ||
295        (srequest->m_type == RubyRequestType_Store_Conditional) ||
296        (srequest->m_type == RubyRequestType_Locked_RMW_Read) ||
297        (srequest->m_type == RubyRequestType_Locked_RMW_Write)) {
298        m_writeRequestTable.erase(line_addr);
299    } else {
300        m_readRequestTable.erase(line_addr);
301    }
302
303    markRemoved();
304}
305
306bool
307Sequencer::handleLlsc(const Address& address, SequencerRequest* request)
308{
309    //
310    // The success flag indicates whether the LLSC operation was successful.
311    // LL ops will always succeed, but SC may fail if the cache line is no
312    // longer locked.
313    //
314    bool success = true;
315    if (request->m_type == RubyRequestType_Store_Conditional) {
316        if (!m_dataCache_ptr->isLocked(address, m_version)) {
317            //
318            // For failed SC requests, indicate the failure to the cpu by
319            // setting the extra data to zero.
320            //
321            request->pkt->req->setExtraData(0);
322            success = false;
323        } else {
324            //
325            // For successful SC requests, indicate the success to the cpu by
326            // setting the extra data to one.
327            //
328            request->pkt->req->setExtraData(1);
329        }
330        //
331        // Independent of success, all SC operations must clear the lock
332        //
333        m_dataCache_ptr->clearLocked(address);
334    } else if (request->m_type == RubyRequestType_Load_Linked) {
335        //
336        // Note: To fully follow Alpha LLSC semantics, should the LL clear any
337        // previously locked cache lines?
338        //
339        m_dataCache_ptr->setLocked(address, m_version);
340    } else if ((m_dataCache_ptr->isTagPresent(address)) &&
341               (m_dataCache_ptr->isLocked(address, m_version))) {
342        //
343        // Normal writes should clear the locked address
344        //
345        m_dataCache_ptr->clearLocked(address);
346    }
347    return success;
348}
349
350void
351Sequencer::writeCallback(const Address& address, DataBlock& data)
352{
353    writeCallback(address, GenericMachineType_NULL, data);
354}
355
356void
357Sequencer::writeCallback(const Address& address,
358                         GenericMachineType mach,
359                         DataBlock& data)
360{
361    writeCallback(address, mach, data, 0, 0, 0);
362}
363
364void
365Sequencer::writeCallback(const Address& address,
366                         GenericMachineType mach,
367                         DataBlock& data,
368                         Time initialRequestTime,
369                         Time forwardRequestTime,
370                         Time firstResponseTime)
371{
372    assert(address == line_address(address));
373    assert(m_writeRequestTable.count(line_address(address)));
374
375    RequestTable::iterator i = m_writeRequestTable.find(address);
376    assert(i != m_writeRequestTable.end());
377    SequencerRequest* request = i->second;
378
379    m_writeRequestTable.erase(i);
380    markRemoved();
381
382    assert((request->m_type == RubyRequestType_ST) ||
383           (request->m_type == RubyRequestType_ATOMIC) ||
384           (request->m_type == RubyRequestType_RMW_Read) ||
385           (request->m_type == RubyRequestType_RMW_Write) ||
386           (request->m_type == RubyRequestType_Load_Linked) ||
387           (request->m_type == RubyRequestType_Store_Conditional) ||
388           (request->m_type == RubyRequestType_Locked_RMW_Read) ||
389           (request->m_type == RubyRequestType_Locked_RMW_Write) ||
390           (request->m_type == RubyRequestType_FLUSH));
391
392
393    //
394    // For Alpha, properly handle LL, SC, and write requests with respect to
395    // locked cache blocks.
396    //
397    // Not valid for Network_test protocl
398    //
399    bool success = true;
400    if(!m_usingNetworkTester)
401        success = handleLlsc(address, request);
402
403    if (request->m_type == RubyRequestType_Locked_RMW_Read) {
404        m_controller->blockOnQueue(address, m_mandatory_q_ptr);
405    } else if (request->m_type == RubyRequestType_Locked_RMW_Write) {
406        m_controller->unblock(address);
407    }
408
409    hitCallback(request, mach, data, success,
410                initialRequestTime, forwardRequestTime, firstResponseTime);
411}
412
413void
414Sequencer::readCallback(const Address& address, DataBlock& data)
415{
416    readCallback(address, GenericMachineType_NULL, data);
417}
418
419void
420Sequencer::readCallback(const Address& address,
421                        GenericMachineType mach,
422                        DataBlock& data)
423{
424    readCallback(address, mach, data, 0, 0, 0);
425}
426
427void
428Sequencer::readCallback(const Address& address,
429                        GenericMachineType mach,
430                        DataBlock& data,
431                        Time initialRequestTime,
432                        Time forwardRequestTime,
433                        Time firstResponseTime)
434{
435    assert(address == line_address(address));
436    assert(m_readRequestTable.count(line_address(address)));
437
438    RequestTable::iterator i = m_readRequestTable.find(address);
439    assert(i != m_readRequestTable.end());
440    SequencerRequest* request = i->second;
441
442    m_readRequestTable.erase(i);
443    markRemoved();
444
445    assert((request->m_type == RubyRequestType_LD) ||
446           (request->m_type == RubyRequestType_IFETCH));
447
448    hitCallback(request, mach, data, true,
449                initialRequestTime, forwardRequestTime, firstResponseTime);
450}
451
452void
453Sequencer::hitCallback(SequencerRequest* srequest,
454                       GenericMachineType mach,
455                       DataBlock& data,
456                       bool success,
457                       Time initialRequestTime,
458                       Time forwardRequestTime,
459                       Time firstResponseTime)
460{
461    PacketPtr pkt = srequest->pkt;
462    Address request_address(pkt->getAddr());
463    Address request_line_address(pkt->getAddr());
464    request_line_address.makeLineAddress();
465    RubyRequestType type = srequest->m_type;
466    Time issued_time = srequest->issue_time;
467
468    // Set this cache entry to the most recently used
469    if (type == RubyRequestType_IFETCH) {
470        m_instCache_ptr->setMRU(request_line_address);
471    } else {
472        m_dataCache_ptr->setMRU(request_line_address);
473    }
474
475    assert(g_system_ptr->getTime() >= issued_time);
476    Time miss_latency = g_system_ptr->getTime() - issued_time;
477
478    // Profile the miss latency for all non-zero demand misses
479    if (miss_latency != 0) {
480        g_system_ptr->getProfiler()->missLatency(miss_latency, type, mach);
481
482        if (mach == GenericMachineType_L1Cache_wCC) {
483            g_system_ptr->getProfiler()->missLatencyWcc(issued_time,
484                                                   initialRequestTime,
485                                                   forwardRequestTime,
486                                                   firstResponseTime,
487                                                   g_system_ptr->getTime());
488        }
489
490        if (mach == GenericMachineType_Directory) {
491            g_system_ptr->getProfiler()->missLatencyDir(issued_time,
492                                                   initialRequestTime,
493                                                   forwardRequestTime,
494                                                   firstResponseTime,
495                                                   g_system_ptr->getTime());
496        }
497
498        DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %d cycles\n",
499                 curTick(), m_version, "Seq",
500                 success ? "Done" : "SC_Failed", "", "",
501                 request_address, miss_latency);
502    }
503
504    // update the data
505    if (g_system_ptr->m_warmup_enabled) {
506        assert(pkt->getPtr<uint8_t>(false) != NULL);
507        data.setData(pkt->getPtr<uint8_t>(false),
508                     request_address.getOffset(), pkt->getSize());
509    } else if (pkt->getPtr<uint8_t>(true) != NULL) {
510        if ((type == RubyRequestType_LD) ||
511            (type == RubyRequestType_IFETCH) ||
512            (type == RubyRequestType_RMW_Read) ||
513            (type == RubyRequestType_Locked_RMW_Read) ||
514            (type == RubyRequestType_Load_Linked)) {
515            memcpy(pkt->getPtr<uint8_t>(true),
516                   data.getData(request_address.getOffset(), pkt->getSize()),
517                   pkt->getSize());
518        } else {
519            data.setData(pkt->getPtr<uint8_t>(true),
520                         request_address.getOffset(), pkt->getSize());
521        }
522    } else {
523        DPRINTF(MemoryAccess,
524                "WARNING.  Data not transfered from Ruby to M5 for type %s\n",
525                RubyRequestType_to_string(type));
526    }
527
528    // If using the RubyTester, update the RubyTester sender state's
529    // subBlock with the recieved data.  The tester will later access
530    // this state.
531    // Note: RubyPort will access it's sender state before the
532    // RubyTester.
533    if (m_usingRubyTester) {
534        RubyPort::SenderState *requestSenderState =
535            safe_cast<RubyPort::SenderState*>(pkt->senderState);
536        RubyTester::SenderState* testerSenderState =
537            safe_cast<RubyTester::SenderState*>(requestSenderState->saved);
538        testerSenderState->subBlock->mergeFrom(data);
539    }
540
541    delete srequest;
542
543    if (g_system_ptr->m_warmup_enabled) {
544        delete pkt;
545        g_system_ptr->m_cache_recorder->enqueueNextFetchRequest();
546    } else if (g_system_ptr->m_cooldown_enabled) {
547        delete pkt;
548        g_system_ptr->m_cache_recorder->enqueueNextFlushRequest();
549    } else {
550        ruby_hit_callback(pkt);
551    }
552}
553
554bool
555Sequencer::empty() const
556{
557    return m_writeRequestTable.empty() && m_readRequestTable.empty();
558}
559
560RequestStatus
561Sequencer::makeRequest(PacketPtr pkt)
562{
563    if (m_outstanding_count >= m_max_outstanding_requests) {
564        return RequestStatus_BufferFull;
565    }
566
567    RubyRequestType primary_type = RubyRequestType_NULL;
568    RubyRequestType secondary_type = RubyRequestType_NULL;
569
570    if (pkt->isLLSC()) {
571        //
572        // Alpha LL/SC instructions need to be handled carefully by the cache
573        // coherence protocol to ensure they follow the proper semantics. In
574        // particular, by identifying the operations as atomic, the protocol
575        // should understand that migratory sharing optimizations should not
576        // be performed (i.e. a load between the LL and SC should not steal
577        // away exclusive permission).
578        //
579        if (pkt->isWrite()) {
580            DPRINTF(RubySequencer, "Issuing SC\n");
581            primary_type = RubyRequestType_Store_Conditional;
582        } else {
583            DPRINTF(RubySequencer, "Issuing LL\n");
584            assert(pkt->isRead());
585            primary_type = RubyRequestType_Load_Linked;
586        }
587        secondary_type = RubyRequestType_ATOMIC;
588    } else if (pkt->req->isLocked()) {
589        //
590        // x86 locked instructions are translated to store cache coherence
591        // requests because these requests should always be treated as read
592        // exclusive operations and should leverage any migratory sharing
593        // optimization built into the protocol.
594        //
595        if (pkt->isWrite()) {
596            DPRINTF(RubySequencer, "Issuing Locked RMW Write\n");
597            primary_type = RubyRequestType_Locked_RMW_Write;
598        } else {
599            DPRINTF(RubySequencer, "Issuing Locked RMW Read\n");
600            assert(pkt->isRead());
601            primary_type = RubyRequestType_Locked_RMW_Read;
602        }
603        secondary_type = RubyRequestType_ST;
604    } else {
605        if (pkt->isRead()) {
606            if (pkt->req->isInstFetch()) {
607                primary_type = secondary_type = RubyRequestType_IFETCH;
608            } else {
609#if THE_ISA == X86_ISA
610                uint32_t flags = pkt->req->getFlags();
611                bool storeCheck = flags &
612                        (TheISA::StoreCheck << TheISA::FlagShift);
613#else
614                bool storeCheck = false;
615#endif // X86_ISA
616                if (storeCheck) {
617                    primary_type = RubyRequestType_RMW_Read;
618                    secondary_type = RubyRequestType_ST;
619                } else {
620                    primary_type = secondary_type = RubyRequestType_LD;
621                }
622            }
623        } else if (pkt->isWrite()) {
624            //
625            // Note: M5 packets do not differentiate ST from RMW_Write
626            //
627            primary_type = secondary_type = RubyRequestType_ST;
628        } else if (pkt->isFlush()) {
629          primary_type = secondary_type = RubyRequestType_FLUSH;
630        } else {
631            panic("Unsupported ruby packet type\n");
632        }
633    }
634
635    RequestStatus status = insertRequest(pkt, primary_type);
636    if (status != RequestStatus_Ready)
637        return status;
638
639    issueRequest(pkt, secondary_type);
640
641    // TODO: issue hardware prefetches here
642    return RequestStatus_Issued;
643}
644
645void
646Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type)
647{
648    assert(pkt != NULL);
649    int proc_id = -1;
650    if (pkt->req->hasContextId()) {
651        proc_id = pkt->req->contextId();
652    }
653
654    // If valid, copy the pc to the ruby request
655    Addr pc = 0;
656    if (pkt->req->hasPC()) {
657        pc = pkt->req->getPC();
658    }
659
660    RubyRequest *msg = new RubyRequest(pkt->getAddr(),
661                                       pkt->getPtr<uint8_t>(true),
662                                       pkt->getSize(), pc, secondary_type,
663                                       RubyAccessMode_Supervisor, pkt,
664                                       PrefetchBit_No, proc_id);
665
666    DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %s\n",
667            curTick(), m_version, "Seq", "Begin", "", "",
668            msg->getPhysicalAddress(),
669            RubyRequestType_to_string(secondary_type));
670
671    Time latency = 0;  // initialzed to an null value
672
673    if (secondary_type == RubyRequestType_IFETCH)
674        latency = m_instCache_ptr->getLatency();
675    else
676        latency = m_dataCache_ptr->getLatency();
677
678    // Send the message to the cache controller
679    assert(latency > 0);
680
681    assert(m_mandatory_q_ptr != NULL);
682    m_mandatory_q_ptr->enqueue(msg, latency);
683}
684
685template <class KEY, class VALUE>
686std::ostream &
687operator<<(ostream &out, const m5::hash_map<KEY, VALUE> &map)
688{
689    typename m5::hash_map<KEY, VALUE>::const_iterator i = map.begin();
690    typename m5::hash_map<KEY, VALUE>::const_iterator end = map.end();
691
692    out << "[";
693    for (; i != end; ++i)
694        out << " " << i->first << "=" << i->second;
695    out << " ]";
696
697    return out;
698}
699
700void
701Sequencer::print(ostream& out) const
702{
703    out << "[Sequencer: " << m_version
704        << ", outstanding requests: " << m_outstanding_count
705        << ", read request table: " << m_readRequestTable
706        << ", write request table: " << m_writeRequestTable
707        << "]";
708}
709
710// this can be called from setState whenever coherence permissions are
711// upgraded when invoked, coherence violations will be checked for the
712// given block
713void
714Sequencer::checkCoherence(const Address& addr)
715{
716#ifdef CHECK_COHERENCE
717    g_system_ptr->checkGlobalCoherenceInvariant(addr);
718#endif
719}
720
721void
722Sequencer::recordRequestType(SequencerRequestType requestType) {
723    DPRINTF(RubyStats, "Recorded statistic: %s\n",
724            SequencerRequestType_to_string(requestType));
725}
726
727
728void
729Sequencer::evictionCallback(const Address& address)
730{
731    ruby_eviction_callback(address);
732}
733