Sequencer.cc revision 8229:78bf55f23338 
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "base/misc.hh"
30#include "base/str.hh"
31#include "cpu/testers/rubytest/RubyTester.hh"
32#include "mem/protocol/Protocol.hh"
33#include "mem/ruby/buffers/MessageBuffer.hh"
34#include "mem/ruby/common/Global.hh"
35#include "mem/ruby/common/SubBlock.hh"
36#include "mem/ruby/profiler/Profiler.hh"
37#include "mem/ruby/recorder/Tracer.hh"
38#include "mem/ruby/slicc_interface/AbstractController.hh"
39#include "mem/ruby/slicc_interface/RubyRequest.hh"
40#include "mem/ruby/system/CacheMemory.hh"
41#include "mem/ruby/system/Sequencer.hh"
42#include "mem/ruby/system/System.hh"
43#include "mem/packet.hh"
44#include "params/RubySequencer.hh"
45
46using namespace std;
47
48Sequencer *
49RubySequencerParams::create()
50{
51    return new Sequencer(this);
52}
53
54Sequencer::Sequencer(const Params *p)
55    : RubyPort(p), deadlockCheckEvent(this)
56{
57    m_store_waiting_on_load_cycles = 0;
58    m_store_waiting_on_store_cycles = 0;
59    m_load_waiting_on_store_cycles = 0;
60    m_load_waiting_on_load_cycles = 0;
61
62    m_outstanding_count = 0;
63
64    m_max_outstanding_requests = 0;
65    m_deadlock_threshold = 0;
66    m_instCache_ptr = NULL;
67    m_dataCache_ptr = NULL;
68
69    m_instCache_ptr = p->icache;
70    m_dataCache_ptr = p->dcache;
71    m_max_outstanding_requests = p->max_outstanding_requests;
72    m_deadlock_threshold = p->deadlock_threshold;
73
74    assert(m_max_outstanding_requests > 0);
75    assert(m_deadlock_threshold > 0);
76    assert(m_instCache_ptr != NULL);
77    assert(m_dataCache_ptr != NULL);
78
79    m_usingNetworkTester = p->using_network_tester;
80}
81
82Sequencer::~Sequencer()
83{
84}
85
86void
87Sequencer::wakeup()
88{
89    // Check for deadlock of any of the requests
90    Time current_time = g_eventQueue_ptr->getTime();
91
92    // Check across all outstanding requests
93    int total_outstanding = 0;
94
95    RequestTable::iterator read = m_readRequestTable.begin();
96    RequestTable::iterator read_end = m_readRequestTable.end();
97    for (; read != read_end; ++read) {
98        SequencerRequest* request = read->second;
99        if (current_time - request->issue_time < m_deadlock_threshold)
100            continue;
101
102        panic("Possible Deadlock detected. Aborting!\n"
103             "version: %d request.paddr: 0x%x m_readRequestTable: %d "
104             "current time: %u issue_time: %d difference: %d\n", m_version,
105             request->ruby_request.m_PhysicalAddress, m_readRequestTable.size(),
106             current_time, request->issue_time,
107             current_time - request->issue_time);
108    }
109
110    RequestTable::iterator write = m_writeRequestTable.begin();
111    RequestTable::iterator write_end = m_writeRequestTable.end();
112    for (; write != write_end; ++write) {
113        SequencerRequest* request = write->second;
114        if (current_time - request->issue_time < m_deadlock_threshold)
115            continue;
116
117        panic("Possible Deadlock detected. Aborting!\n"
118             "version: %d request.paddr: 0x%x m_writeRequestTable: %d "
119             "current time: %u issue_time: %d difference: %d\n", m_version,
120             request->ruby_request.m_PhysicalAddress, m_writeRequestTable.size(),
121             current_time, request->issue_time,
122             current_time - request->issue_time);
123    }
124
125    total_outstanding += m_writeRequestTable.size();
126    total_outstanding += m_readRequestTable.size();
127
128    assert(m_outstanding_count == total_outstanding);
129
130    if (m_outstanding_count > 0) {
131        // If there are still outstanding requests, keep checking
132        schedule(deadlockCheckEvent,
133                 m_deadlock_threshold * g_eventQueue_ptr->getClock() +
134                 curTick());
135    }
136}
137
138void
139Sequencer::printStats(ostream & out) const
140{
141    out << "Sequencer: " << m_name << endl
142        << "  store_waiting_on_load_cycles: "
143        << m_store_waiting_on_load_cycles << endl
144        << "  store_waiting_on_store_cycles: "
145        << m_store_waiting_on_store_cycles << endl
146        << "  load_waiting_on_load_cycles: "
147        << m_load_waiting_on_load_cycles << endl
148        << "  load_waiting_on_store_cycles: "
149        << m_load_waiting_on_store_cycles << endl;
150}
151
152void
153Sequencer::printProgress(ostream& out) const
154{
155#if 0
156    int total_demand = 0;
157    out << "Sequencer Stats Version " << m_version << endl;
158    out << "Current time = " << g_eventQueue_ptr->getTime() << endl;
159    out << "---------------" << endl;
160    out << "outstanding requests" << endl;
161
162    out << "proc " << m_Read
163        << " version Requests = " << m_readRequestTable.size() << endl;
164
165    // print the request table
166    RequestTable::iterator read = m_readRequestTable.begin();
167    RequestTable::iterator read_end = m_readRequestTable.end();
168    for (; read != read_end; ++read) {
169        SequencerRequest* request = read->second;
170        out << "\tRequest[ " << i << " ] = " << request->type
171            << " Address " << rkeys[i]
172            << " Posted " << request->issue_time
173            << " PF " << PrefetchBit_No << endl;
174        total_demand++;
175    }
176
177    out << "proc " << m_version
178        << " Write Requests = " << m_writeRequestTable.size << endl;
179
180    // print the request table
181    RequestTable::iterator write = m_writeRequestTable.begin();
182    RequestTable::iterator write_end = m_writeRequestTable.end();
183    for (; write != write_end; ++write) {
184        SequencerRequest* request = write->second;
185        out << "\tRequest[ " << i << " ] = " << request.getType()
186            << " Address " << wkeys[i]
187            << " Posted " << request.getTime()
188            << " PF " << request.getPrefetch() << endl;
189        if (request.getPrefetch() == PrefetchBit_No) {
190            total_demand++;
191        }
192    }
193
194    out << endl;
195
196    out << "Total Number Outstanding: " << m_outstanding_count << endl
197        << "Total Number Demand     : " << total_demand << endl
198        << "Total Number Prefetches : " << m_outstanding_count - total_demand
199        << endl << endl << endl;
200#endif
201}
202
203void
204Sequencer::printConfig(ostream& out) const
205{
206    out << "Seqeuncer config: " << m_name << endl
207        << "  controller: " << m_controller->getName() << endl
208        << "  version: " << m_version << endl
209        << "  max_outstanding_requests: " << m_max_outstanding_requests << endl
210        << "  deadlock_threshold: " << m_deadlock_threshold << endl;
211}
212
213// Insert the request on the correct request table.  Return true if
214// the entry was already present.
215bool
216Sequencer::insertRequest(SequencerRequest* request)
217{
218    int total_outstanding =
219        m_writeRequestTable.size() + m_readRequestTable.size();
220
221    assert(m_outstanding_count == total_outstanding);
222
223    // See if we should schedule a deadlock check
224    if (deadlockCheckEvent.scheduled() == false) {
225        schedule(deadlockCheckEvent, m_deadlock_threshold + curTick());
226    }
227
228    Address line_addr(request->ruby_request.m_PhysicalAddress);
229    line_addr.makeLineAddress();
230    if ((request->ruby_request.m_Type == RubyRequestType_ST) ||
231        (request->ruby_request.m_Type == RubyRequestType_ATOMIC) ||
232        (request->ruby_request.m_Type == RubyRequestType_RMW_Read) ||
233        (request->ruby_request.m_Type == RubyRequestType_RMW_Write) ||
234        (request->ruby_request.m_Type == RubyRequestType_Load_Linked) ||
235        (request->ruby_request.m_Type == RubyRequestType_Store_Conditional) ||
236        (request->ruby_request.m_Type == RubyRequestType_Locked_RMW_Read) ||
237        (request->ruby_request.m_Type == RubyRequestType_Locked_RMW_Write) ||
238        (request->ruby_request.m_Type == RubyRequestType_FLUSH)) {
239        pair<RequestTable::iterator, bool> r =
240            m_writeRequestTable.insert(RequestTable::value_type(line_addr, 0));
241        bool success = r.second;
242        RequestTable::iterator i = r.first;
243        if (!success) {
244            i->second = request;
245            // return true;
246
247            // drh5: isn't this an error?  do you lose the initial request?
248            assert(0);
249        }
250        i->second = request;
251        m_outstanding_count++;
252    } else {
253        pair<RequestTable::iterator, bool> r =
254            m_readRequestTable.insert(RequestTable::value_type(line_addr, 0));
255        bool success = r.second;
256        RequestTable::iterator i = r.first;
257        if (!success) {
258            i->second = request;
259            // return true;
260
261            // drh5: isn't this an error?  do you lose the initial request?
262            assert(0);
263        }
264        i->second = request;
265        m_outstanding_count++;
266    }
267
268    g_system_ptr->getProfiler()->sequencerRequests(m_outstanding_count);
269
270    total_outstanding = m_writeRequestTable.size() + m_readRequestTable.size();
271    assert(m_outstanding_count == total_outstanding);
272
273    return false;
274}
275
276void
277Sequencer::markRemoved()
278{
279    m_outstanding_count--;
280    assert(m_outstanding_count ==
281           m_writeRequestTable.size() + m_readRequestTable.size());
282}
283
284void
285Sequencer::removeRequest(SequencerRequest* srequest)
286{
287    assert(m_outstanding_count ==
288           m_writeRequestTable.size() + m_readRequestTable.size());
289
290    const RubyRequest & ruby_request = srequest->ruby_request;
291    Address line_addr(ruby_request.m_PhysicalAddress);
292    line_addr.makeLineAddress();
293    if ((ruby_request.m_Type == RubyRequestType_ST) ||
294        (ruby_request.m_Type == RubyRequestType_RMW_Read) ||
295        (ruby_request.m_Type == RubyRequestType_RMW_Write) ||
296        (ruby_request.m_Type == RubyRequestType_Load_Linked) ||
297        (ruby_request.m_Type == RubyRequestType_Store_Conditional) ||
298        (ruby_request.m_Type == RubyRequestType_Locked_RMW_Read) ||
299        (ruby_request.m_Type == RubyRequestType_Locked_RMW_Write)) {
300        m_writeRequestTable.erase(line_addr);
301    } else {
302        m_readRequestTable.erase(line_addr);
303    }
304
305    markRemoved();
306}
307
308bool
309Sequencer::handleLlsc(const Address& address, SequencerRequest* request)
310{
311    //
312    // The success flag indicates whether the LLSC operation was successful.
313    // LL ops will always succeed, but SC may fail if the cache line is no
314    // longer locked.
315    //
316    bool success = true;
317    if (request->ruby_request.m_Type == RubyRequestType_Store_Conditional) {
318        if (!m_dataCache_ptr->isLocked(address, m_version)) {
319            //
320            // For failed SC requests, indicate the failure to the cpu by
321            // setting the extra data to zero.
322            //
323            request->ruby_request.pkt->req->setExtraData(0);
324            success = false;
325        } else {
326            //
327            // For successful SC requests, indicate the success to the cpu by
328            // setting the extra data to one.
329            //
330            request->ruby_request.pkt->req->setExtraData(1);
331        }
332        //
333        // Independent of success, all SC operations must clear the lock
334        //
335        m_dataCache_ptr->clearLocked(address);
336    } else if (request->ruby_request.m_Type == RubyRequestType_Load_Linked) {
337        //
338        // Note: To fully follow Alpha LLSC semantics, should the LL clear any
339        // previously locked cache lines?
340        //
341        m_dataCache_ptr->setLocked(address, m_version);
342    } else if ((m_dataCache_ptr->isTagPresent(address)) && (m_dataCache_ptr->isLocked(address, m_version))) {
343        //
344        // Normal writes should clear the locked address
345        //
346        m_dataCache_ptr->clearLocked(address);
347    }
348    return success;
349}
350
351void
352Sequencer::writeCallback(const Address& address, DataBlock& data)
353{
354    writeCallback(address, GenericMachineType_NULL, data);
355}
356
357void
358Sequencer::writeCallback(const Address& address,
359                         GenericMachineType mach,
360                         DataBlock& data)
361{
362    writeCallback(address, mach, data, 0, 0, 0);
363}
364
365void
366Sequencer::writeCallback(const Address& address,
367                         GenericMachineType mach,
368                         DataBlock& data,
369                         Time initialRequestTime,
370                         Time forwardRequestTime,
371                         Time firstResponseTime)
372{
373    assert(address == line_address(address));
374    assert(m_writeRequestTable.count(line_address(address)));
375
376    RequestTable::iterator i = m_writeRequestTable.find(address);
377    assert(i != m_writeRequestTable.end());
378    SequencerRequest* request = i->second;
379
380    m_writeRequestTable.erase(i);
381    markRemoved();
382
383    assert((request->ruby_request.m_Type == RubyRequestType_ST) ||
384           (request->ruby_request.m_Type == RubyRequestType_ATOMIC) ||
385           (request->ruby_request.m_Type == RubyRequestType_RMW_Read) ||
386           (request->ruby_request.m_Type == RubyRequestType_RMW_Write) ||
387           (request->ruby_request.m_Type == RubyRequestType_Load_Linked) ||
388           (request->ruby_request.m_Type == RubyRequestType_Store_Conditional) ||
389           (request->ruby_request.m_Type == RubyRequestType_Locked_RMW_Read) ||
390           (request->ruby_request.m_Type == RubyRequestType_Locked_RMW_Write) ||
391           (request->ruby_request.m_Type == RubyRequestType_FLUSH));
392
393
394    //
395    // For Alpha, properly handle LL, SC, and write requests with respect to
396    // locked cache blocks.
397    //
398    // Not valid for Network_test protocl
399    //
400    bool success = true;
401    if(!m_usingNetworkTester)
402        success = handleLlsc(address, request);
403
404    if (request->ruby_request.m_Type == RubyRequestType_Locked_RMW_Read) {
405        m_controller->blockOnQueue(address, m_mandatory_q_ptr);
406    } else if (request->ruby_request.m_Type == RubyRequestType_Locked_RMW_Write) {
407        m_controller->unblock(address);
408    }
409
410    hitCallback(request, mach, data, success,
411                initialRequestTime, forwardRequestTime, firstResponseTime);
412}
413
414void
415Sequencer::readCallback(const Address& address, DataBlock& data)
416{
417    readCallback(address, GenericMachineType_NULL, data);
418}
419
420void
421Sequencer::readCallback(const Address& address,
422                        GenericMachineType mach,
423                        DataBlock& data)
424{
425    readCallback(address, mach, data, 0, 0, 0);
426}
427
428void
429Sequencer::readCallback(const Address& address,
430                        GenericMachineType mach,
431                        DataBlock& data,
432                        Time initialRequestTime,
433                        Time forwardRequestTime,
434                        Time firstResponseTime)
435{
436    assert(address == line_address(address));
437    assert(m_readRequestTable.count(line_address(address)));
438
439    RequestTable::iterator i = m_readRequestTable.find(address);
440    assert(i != m_readRequestTable.end());
441    SequencerRequest* request = i->second;
442
443    m_readRequestTable.erase(i);
444    markRemoved();
445
446    assert((request->ruby_request.m_Type == RubyRequestType_LD) ||
447           (request->ruby_request.m_Type == RubyRequestType_IFETCH));
448
449    hitCallback(request, mach, data, true,
450                initialRequestTime, forwardRequestTime, firstResponseTime);
451}
452
453void
454Sequencer::hitCallback(SequencerRequest* srequest,
455                       GenericMachineType mach,
456                       DataBlock& data,
457                       bool success,
458                       Time initialRequestTime,
459                       Time forwardRequestTime,
460                       Time firstResponseTime)
461{
462    const RubyRequest & ruby_request = srequest->ruby_request;
463    Address request_address(ruby_request.m_PhysicalAddress);
464    Address request_line_address(ruby_request.m_PhysicalAddress);
465    request_line_address.makeLineAddress();
466    RubyRequestType type = ruby_request.m_Type;
467    Time issued_time = srequest->issue_time;
468
469    // Set this cache entry to the most recently used
470    if (type == RubyRequestType_IFETCH) {
471        if (m_instCache_ptr->isTagPresent(request_line_address))
472            m_instCache_ptr->setMRU(request_line_address);
473    } else {
474        if (m_dataCache_ptr->isTagPresent(request_line_address))
475            m_dataCache_ptr->setMRU(request_line_address);
476    }
477
478    assert(g_eventQueue_ptr->getTime() >= issued_time);
479    Time miss_latency = g_eventQueue_ptr->getTime() - issued_time;
480
481    // Profile the miss latency for all non-zero demand misses
482    if (miss_latency != 0) {
483        g_system_ptr->getProfiler()->missLatency(miss_latency, type, mach);
484
485        if (mach == GenericMachineType_L1Cache_wCC) {
486            g_system_ptr->getProfiler()->missLatencyWcc(issued_time,
487                                                   initialRequestTime,
488                                                   forwardRequestTime,
489                                                   firstResponseTime,
490                                                   g_eventQueue_ptr->getTime());
491        }
492
493        if (mach == GenericMachineType_Directory) {
494            g_system_ptr->getProfiler()->missLatencyDir(issued_time,
495                                                   initialRequestTime,
496                                                   forwardRequestTime,
497                                                   firstResponseTime,
498                                                   g_eventQueue_ptr->getTime());
499        }
500
501        DPRINTFR(ProtocolTrace, "%7s %3s %10s%20s %6s>%-6s %s %d cycles\n",
502            g_eventQueue_ptr->getTime(), m_version, "Seq",
503            success ? "Done" : "SC_Failed", "", "",
504            ruby_request.m_PhysicalAddress, miss_latency);
505    }
506#if 0
507    if (request.getPrefetch() == PrefetchBit_Yes) {
508        return; // Ignore the prefetch
509    }
510#endif
511
512    // update the data
513    if (ruby_request.data != NULL) {
514        if ((type == RubyRequestType_LD) ||
515            (type == RubyRequestType_IFETCH) ||
516            (type == RubyRequestType_RMW_Read) ||
517            (type == RubyRequestType_Locked_RMW_Read) ||
518            (type == RubyRequestType_Load_Linked)) {
519            memcpy(ruby_request.data,
520                   data.getData(request_address.getOffset(), ruby_request.m_Size),
521                   ruby_request.m_Size);
522        } else {
523            data.setData(ruby_request.data, request_address.getOffset(),
524                         ruby_request.m_Size);
525        }
526    } else {
527        DPRINTF(MemoryAccess,
528                "WARNING.  Data not transfered from Ruby to M5 for type %s\n",
529                RubyRequestType_to_string(type));
530    }
531
532    // If using the RubyTester, update the RubyTester sender state's
533    // subBlock with the recieved data.  The tester will later access
534    // this state.
535    // Note: RubyPort will access it's sender state before the
536    // RubyTester.
537    if (m_usingRubyTester) {
538        RubyPort::SenderState *requestSenderState =
539            safe_cast<RubyPort::SenderState*>(ruby_request.pkt->senderState);
540        RubyTester::SenderState* testerSenderState =
541            safe_cast<RubyTester::SenderState*>(requestSenderState->saved);
542        testerSenderState->subBlock->mergeFrom(data);
543    }
544
545    ruby_hit_callback(ruby_request.pkt);
546    delete srequest;
547}
548
549// Returns true if the sequencer already has a load or store outstanding
550RequestStatus
551Sequencer::getRequestStatus(const RubyRequest& request)
552{
553    bool is_outstanding_store =
554        !!m_writeRequestTable.count(line_address(request.m_PhysicalAddress));
555    bool is_outstanding_load =
556        !!m_readRequestTable.count(line_address(request.m_PhysicalAddress));
557    if (is_outstanding_store) {
558        if ((request.m_Type == RubyRequestType_LD) ||
559            (request.m_Type == RubyRequestType_IFETCH) ||
560            (request.m_Type == RubyRequestType_RMW_Read)) {
561            m_store_waiting_on_load_cycles++;
562        } else {
563            m_store_waiting_on_store_cycles++;
564        }
565        return RequestStatus_Aliased;
566    } else if (is_outstanding_load) {
567        if ((request.m_Type == RubyRequestType_ST) ||
568            (request.m_Type == RubyRequestType_RMW_Write)) {
569            m_load_waiting_on_store_cycles++;
570        } else {
571            m_load_waiting_on_load_cycles++;
572        }
573        return RequestStatus_Aliased;
574    }
575
576    if (m_outstanding_count >= m_max_outstanding_requests) {
577        return RequestStatus_BufferFull;
578    }
579
580    return RequestStatus_Ready;
581}
582
583bool
584Sequencer::empty() const
585{
586    return m_writeRequestTable.empty() && m_readRequestTable.empty();
587}
588
589RequestStatus
590Sequencer::makeRequest(const RubyRequest &request)
591{
592    assert(request.m_PhysicalAddress.getOffset() + request.m_Size <=
593           RubySystem::getBlockSizeBytes());
594    RequestStatus status = getRequestStatus(request);
595    if (status != RequestStatus_Ready)
596        return status;
597
598    SequencerRequest *srequest =
599        new SequencerRequest(request, g_eventQueue_ptr->getTime());
600    bool found = insertRequest(srequest);
601    if (found) {
602        panic("Sequencer::makeRequest should never be called if the "
603              "request is already outstanding\n");
604        return RequestStatus_NULL;
605    }
606
607    issueRequest(request);
608
609    // TODO: issue hardware prefetches here
610    return RequestStatus_Issued;
611}
612
613void
614Sequencer::issueRequest(const RubyRequest& request)
615{
616    // TODO: Eliminate RubyRequest being copied again.
617
618    RubyRequestType ctype;
619    switch(request.m_Type) {
620      case RubyRequestType_IFETCH:
621        ctype = RubyRequestType_IFETCH;
622        break;
623      case RubyRequestType_LD:
624        ctype = RubyRequestType_LD;
625        break;
626      case RubyRequestType_FLUSH:
627        ctype = RubyRequestType_FLUSH;
628        break;
629      case RubyRequestType_ST:
630      case RubyRequestType_RMW_Read:
631      case RubyRequestType_RMW_Write:
632      //
633      // x86 locked instructions are translated to store cache coherence
634      // requests because these requests should always be treated as read
635      // exclusive operations and should leverage any migratory sharing
636      // optimization built into the protocol.
637      //
638      case RubyRequestType_Locked_RMW_Read:
639      case RubyRequestType_Locked_RMW_Write:
640        ctype = RubyRequestType_ST;
641        break;
642      //
643      // Alpha LL/SC instructions need to be handled carefully by the cache
644      // coherence protocol to ensure they follow the proper semantics.  In
645      // particular, by identifying the operations as atomic, the protocol
646      // should understand that migratory sharing optimizations should not be
647      // performed (i.e. a load between the LL and SC should not steal away
648      // exclusive permission).
649      //
650      case RubyRequestType_Load_Linked:
651      case RubyRequestType_Store_Conditional:
652      case RubyRequestType_ATOMIC:
653        ctype = RubyRequestType_ATOMIC;
654        break;
655      default:
656        assert(0);
657    }
658
659    RubyAccessMode amtype;
660    switch(request.m_AccessMode){
661      case RubyAccessMode_User:
662        amtype = RubyAccessMode_User;
663        break;
664      case RubyAccessMode_Supervisor:
665        amtype = RubyAccessMode_Supervisor;
666        break;
667      case RubyAccessMode_Device:
668        amtype = RubyAccessMode_User;
669        break;
670      default:
671        assert(0);
672    }
673
674    Address line_addr(request.m_PhysicalAddress);
675    line_addr.makeLineAddress();
676    int proc_id = -1;
677    if (request.pkt != NULL && request.pkt->req->hasContextId()) {
678        proc_id = request.pkt->req->contextId();
679    }
680    RubyRequest *msg = new RubyRequest(request.m_PhysicalAddress.getAddress(),
681                                       request.data, request.m_Size,
682                                       request.m_ProgramCounter.getAddress(),
683                                       ctype, amtype, request.pkt,
684                                       PrefetchBit_No, proc_id);
685
686    DPRINTFR(ProtocolTrace, "%7s %3s %10s%20s %6s>%-6s %s %s\n",
687        g_eventQueue_ptr->getTime(), m_version, "Seq", "Begin", "", "",
688        request.m_PhysicalAddress, RubyRequestType_to_string(request.m_Type));
689
690    Time latency = 0;  // initialzed to an null value
691
692    if (request.m_Type == RubyRequestType_IFETCH)
693        latency = m_instCache_ptr->getLatency();
694    else
695        latency = m_dataCache_ptr->getLatency();
696
697    // Send the message to the cache controller
698    assert(latency > 0);
699
700    assert(m_mandatory_q_ptr != NULL);
701    m_mandatory_q_ptr->enqueue(msg, latency);
702}
703
704#if 0
705bool
706Sequencer::tryCacheAccess(const Address& addr, RubyRequestType type,
707                          RubyAccessMode access_mode,
708                          int size, DataBlock*& data_ptr)
709{
710    CacheMemory *cache =
711        (type == RubyRequestType_IFETCH) ? m_instCache_ptr : m_dataCache_ptr;
712
713    return cache->tryCacheAccess(line_address(addr), type, data_ptr);
714}
715#endif
716
717template <class KEY, class VALUE>
718std::ostream &
719operator<<(ostream &out, const m5::hash_map<KEY, VALUE> &map)
720{
721    typename m5::hash_map<KEY, VALUE>::const_iterator i = map.begin();
722    typename m5::hash_map<KEY, VALUE>::const_iterator end = map.end();
723
724    out << "[";
725    for (; i != end; ++i)
726        out << " " << i->first << "=" << i->second;
727    out << " ]";
728
729    return out;
730}
731
732void
733Sequencer::print(ostream& out) const
734{
735    out << "[Sequencer: " << m_version
736        << ", outstanding requests: " << m_outstanding_count
737        << ", read request table: " << m_readRequestTable
738        << ", write request table: " << m_writeRequestTable
739        << "]";
740}
741
742// this can be called from setState whenever coherence permissions are
743// upgraded when invoked, coherence violations will be checked for the
744// given block
745void
746Sequencer::checkCoherence(const Address& addr)
747{
748#ifdef CHECK_COHERENCE
749    g_system_ptr->checkGlobalCoherenceInvariant(addr);
750#endif
751}
752