Sequencer.cc revision 7908:4e83ebb67794 
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "base/str.hh"
30#include "base/misc.hh"
31#include "cpu/testers/rubytest/RubyTester.hh"
32#include "mem/protocol/CacheMsg.hh"
33#include "mem/protocol/Protocol.hh"
34#include "mem/protocol/Protocol.hh"
35#include "mem/ruby/buffers/MessageBuffer.hh"
36#include "mem/ruby/common/Global.hh"
37#include "mem/ruby/common/SubBlock.hh"
38#include "mem/ruby/libruby.hh"
39#include "mem/ruby/profiler/Profiler.hh"
40#include "mem/ruby/recorder/Tracer.hh"
41#include "mem/ruby/slicc_interface/AbstractController.hh"
42#include "mem/ruby/system/CacheMemory.hh"
43#include "mem/ruby/system/Sequencer.hh"
44#include "mem/ruby/system/System.hh"
45#include "mem/packet.hh"
46#include "params/RubySequencer.hh"
47
48using namespace std;
49
50Sequencer *
51RubySequencerParams::create()
52{
53    return new Sequencer(this);
54}
55
56Sequencer::Sequencer(const Params *p)
57    : RubyPort(p), deadlockCheckEvent(this)
58{
59    m_store_waiting_on_load_cycles = 0;
60    m_store_waiting_on_store_cycles = 0;
61    m_load_waiting_on_store_cycles = 0;
62    m_load_waiting_on_load_cycles = 0;
63
64    m_outstanding_count = 0;
65
66    m_max_outstanding_requests = 0;
67    m_deadlock_threshold = 0;
68    m_instCache_ptr = NULL;
69    m_dataCache_ptr = NULL;
70
71    m_instCache_ptr = p->icache;
72    m_dataCache_ptr = p->dcache;
73    m_max_outstanding_requests = p->max_outstanding_requests;
74    m_deadlock_threshold = p->deadlock_threshold;
75    m_usingRubyTester = p->using_ruby_tester;
76
77    assert(m_max_outstanding_requests > 0);
78    assert(m_deadlock_threshold > 0);
79    assert(m_instCache_ptr != NULL);
80    assert(m_dataCache_ptr != NULL);
81}
82
83Sequencer::~Sequencer()
84{
85}
86
87void
88Sequencer::wakeup()
89{
90    // Check for deadlock of any of the requests
91    Time current_time = g_eventQueue_ptr->getTime();
92
93    // Check across all outstanding requests
94    int total_outstanding = 0;
95
96    RequestTable::iterator read = m_readRequestTable.begin();
97    RequestTable::iterator read_end = m_readRequestTable.end();
98    for (; read != read_end; ++read) {
99        SequencerRequest* request = read->second;
100        if (current_time - request->issue_time < m_deadlock_threshold)
101            continue;
102
103        panic("Possible Deadlock detected. Aborting!\n"
104             "version: %d request.paddr: %d m_readRequestTable: %d "
105             "current time: %u issue_time: %d difference: %d\n", m_version,
106             request->ruby_request.paddr, m_readRequestTable.size(),
107             current_time, request->issue_time,
108             current_time - request->issue_time);
109    }
110
111    RequestTable::iterator write = m_writeRequestTable.begin();
112    RequestTable::iterator write_end = m_writeRequestTable.end();
113    for (; write != write_end; ++write) {
114        SequencerRequest* request = write->second;
115        if (current_time - request->issue_time < m_deadlock_threshold)
116            continue;
117
118        panic("Possible Deadlock detected. Aborting!\n"
119             "version: %d request.paddr: %d m_writeRequestTable: %d "
120             "current time: %u issue_time: %d difference: %d\n", m_version,
121             request->ruby_request.paddr, m_writeRequestTable.size(),
122             current_time, request->issue_time,
123             current_time - request->issue_time);
124    }
125
126    total_outstanding += m_writeRequestTable.size();
127    total_outstanding += m_readRequestTable.size();
128
129    assert(m_outstanding_count == total_outstanding);
130
131    if (m_outstanding_count > 0) {
132        // If there are still outstanding requests, keep checking
133        schedule(deadlockCheckEvent,
134                 m_deadlock_threshold * g_eventQueue_ptr->getClock() +
135                 curTick());
136    }
137}
138
139void
140Sequencer::printStats(ostream & out) const
141{
142    out << "Sequencer: " << m_name << endl
143        << "  store_waiting_on_load_cycles: "
144        << m_store_waiting_on_load_cycles << endl
145        << "  store_waiting_on_store_cycles: "
146        << m_store_waiting_on_store_cycles << endl
147        << "  load_waiting_on_load_cycles: "
148        << m_load_waiting_on_load_cycles << endl
149        << "  load_waiting_on_store_cycles: "
150        << m_load_waiting_on_store_cycles << endl;
151}
152
153void
154Sequencer::printProgress(ostream& out) const
155{
156#if 0
157    int total_demand = 0;
158    out << "Sequencer Stats Version " << m_version << endl;
159    out << "Current time = " << g_eventQueue_ptr->getTime() << endl;
160    out << "---------------" << endl;
161    out << "outstanding requests" << endl;
162
163    out << "proc " << m_Read
164        << " version Requests = " << m_readRequestTable.size() << endl;
165
166    // print the request table
167    RequestTable::iterator read = m_readRequestTable.begin();
168    RequestTable::iterator read_end = m_readRequestTable.end();
169    for (; read != read_end; ++read) {
170        SequencerRequest* request = read->second;
171        out << "\tRequest[ " << i << " ] = " << request->type
172            << " Address " << rkeys[i]
173            << " Posted " << request->issue_time
174            << " PF " << PrefetchBit_No << endl;
175        total_demand++;
176    }
177
178    out << "proc " << m_version
179        << " Write Requests = " << m_writeRequestTable.size << endl;
180
181    // print the request table
182    RequestTable::iterator write = m_writeRequestTable.begin();
183    RequestTable::iterator write_end = m_writeRequestTable.end();
184    for (; write != write_end; ++write) {
185        SequencerRequest* request = write->second;
186        out << "\tRequest[ " << i << " ] = " << request.getType()
187            << " Address " << wkeys[i]
188            << " Posted " << request.getTime()
189            << " PF " << request.getPrefetch() << endl;
190        if (request.getPrefetch() == PrefetchBit_No) {
191            total_demand++;
192        }
193    }
194
195    out << endl;
196
197    out << "Total Number Outstanding: " << m_outstanding_count << endl
198        << "Total Number Demand     : " << total_demand << endl
199        << "Total Number Prefetches : " << m_outstanding_count - total_demand
200        << endl << endl << endl;
201#endif
202}
203
204void
205Sequencer::printConfig(ostream& out) const
206{
207    out << "Seqeuncer config: " << m_name << endl
208        << "  controller: " << m_controller->getName() << endl
209        << "  version: " << m_version << endl
210        << "  max_outstanding_requests: " << m_max_outstanding_requests << endl
211        << "  deadlock_threshold: " << m_deadlock_threshold << endl;
212}
213
214// Insert the request on the correct request table.  Return true if
215// the entry was already present.
216bool
217Sequencer::insertRequest(SequencerRequest* request)
218{
219    int total_outstanding =
220        m_writeRequestTable.size() + m_readRequestTable.size();
221
222    assert(m_outstanding_count == total_outstanding);
223
224    // See if we should schedule a deadlock check
225    if (deadlockCheckEvent.scheduled() == false) {
226        schedule(deadlockCheckEvent, m_deadlock_threshold + curTick());
227    }
228
229    Address line_addr(request->ruby_request.paddr);
230    line_addr.makeLineAddress();
231    if ((request->ruby_request.type == RubyRequestType_ST) ||
232        (request->ruby_request.type == RubyRequestType_RMW_Read) ||
233        (request->ruby_request.type == RubyRequestType_RMW_Write) ||
234        (request->ruby_request.type == RubyRequestType_Load_Linked) ||
235        (request->ruby_request.type == RubyRequestType_Store_Conditional) ||
236        (request->ruby_request.type == RubyRequestType_Locked_RMW_Read) ||
237        (request->ruby_request.type == RubyRequestType_Locked_RMW_Write)) {
238        pair<RequestTable::iterator, bool> r =
239            m_writeRequestTable.insert(RequestTable::value_type(line_addr, 0));
240        bool success = r.second;
241        RequestTable::iterator i = r.first;
242        if (!success) {
243            i->second = request;
244            // return true;
245
246            // drh5: isn't this an error?  do you lose the initial request?
247            assert(0);
248        }
249        i->second = request;
250        m_outstanding_count++;
251    } else {
252        pair<RequestTable::iterator, bool> r =
253            m_readRequestTable.insert(RequestTable::value_type(line_addr, 0));
254        bool success = r.second;
255        RequestTable::iterator i = r.first;
256        if (!success) {
257            i->second = request;
258            // return true;
259
260            // drh5: isn't this an error?  do you lose the initial request?
261            assert(0);
262        }
263        i->second = request;
264        m_outstanding_count++;
265    }
266
267    g_system_ptr->getProfiler()->sequencerRequests(m_outstanding_count);
268
269    total_outstanding = m_writeRequestTable.size() + m_readRequestTable.size();
270    assert(m_outstanding_count == total_outstanding);
271
272    return false;
273}
274
275void
276Sequencer::markRemoved()
277{
278    m_outstanding_count--;
279    assert(m_outstanding_count ==
280           m_writeRequestTable.size() + m_readRequestTable.size());
281}
282
283void
284Sequencer::removeRequest(SequencerRequest* srequest)
285{
286    assert(m_outstanding_count ==
287           m_writeRequestTable.size() + m_readRequestTable.size());
288
289    const RubyRequest & ruby_request = srequest->ruby_request;
290    Address line_addr(ruby_request.paddr);
291    line_addr.makeLineAddress();
292    if ((ruby_request.type == RubyRequestType_ST) ||
293        (ruby_request.type == RubyRequestType_RMW_Read) ||
294        (ruby_request.type == RubyRequestType_RMW_Write) ||
295        (ruby_request.type == RubyRequestType_Load_Linked) ||
296        (ruby_request.type == RubyRequestType_Store_Conditional) ||
297        (ruby_request.type == RubyRequestType_Locked_RMW_Read) ||
298        (ruby_request.type == RubyRequestType_Locked_RMW_Write)) {
299        m_writeRequestTable.erase(line_addr);
300    } else {
301        m_readRequestTable.erase(line_addr);
302    }
303
304    markRemoved();
305}
306
307bool
308Sequencer::handleLlsc(const Address& address, SequencerRequest* request)
309{
310    //
311    // The success flag indicates whether the LLSC operation was successful.
312    // LL ops will always succeed, but SC may fail if the cache line is no
313    // longer locked.
314    //
315    bool success = true;
316    if (request->ruby_request.type == RubyRequestType_Store_Conditional) {
317        if (!m_dataCache_ptr->isLocked(address, m_version)) {
318            //
319            // For failed SC requests, indicate the failure to the cpu by
320            // setting the extra data to zero.
321            //
322            request->ruby_request.pkt->req->setExtraData(0);
323            success = false;
324        } else {
325            //
326            // For successful SC requests, indicate the success to the cpu by
327            // setting the extra data to one.
328            //
329            request->ruby_request.pkt->req->setExtraData(1);
330        }
331        //
332        // Independent of success, all SC operations must clear the lock
333        //
334        m_dataCache_ptr->clearLocked(address);
335    } else if (request->ruby_request.type == RubyRequestType_Load_Linked) {
336        //
337        // Note: To fully follow Alpha LLSC semantics, should the LL clear any
338        // previously locked cache lines?
339        //
340        m_dataCache_ptr->setLocked(address, m_version);
341    } else if (m_dataCache_ptr->isLocked(address, m_version)) {
342        //
343        // Normal writes should clear the locked address
344        //
345        m_dataCache_ptr->clearLocked(address);
346    }
347    return success;
348}
349
350void
351Sequencer::writeCallback(const Address& address, DataBlock& data)
352{
353    writeCallback(address, GenericMachineType_NULL, data);
354}
355
356void
357Sequencer::writeCallback(const Address& address,
358                         GenericMachineType mach,
359                         DataBlock& data)
360{
361    writeCallback(address, mach, data, 0, 0, 0);
362}
363
364void
365Sequencer::writeCallback(const Address& address,
366                         GenericMachineType mach,
367                         DataBlock& data,
368                         Time initialRequestTime,
369                         Time forwardRequestTime,
370                         Time firstResponseTime)
371{
372    assert(address == line_address(address));
373    assert(m_writeRequestTable.count(line_address(address)));
374
375    RequestTable::iterator i = m_writeRequestTable.find(address);
376    assert(i != m_writeRequestTable.end());
377    SequencerRequest* request = i->second;
378
379    m_writeRequestTable.erase(i);
380    markRemoved();
381
382    assert((request->ruby_request.type == RubyRequestType_ST) ||
383           (request->ruby_request.type == RubyRequestType_RMW_Read) ||
384           (request->ruby_request.type == RubyRequestType_RMW_Write) ||
385           (request->ruby_request.type == RubyRequestType_Load_Linked) ||
386           (request->ruby_request.type == RubyRequestType_Store_Conditional) ||
387           (request->ruby_request.type == RubyRequestType_Locked_RMW_Read) ||
388           (request->ruby_request.type == RubyRequestType_Locked_RMW_Write));
389
390    //
391    // For Alpha, properly handle LL, SC, and write requests with respect to
392    // locked cache blocks.
393    //
394    bool success = handleLlsc(address, request);
395
396    if (request->ruby_request.type == RubyRequestType_Locked_RMW_Read) {
397        m_controller->blockOnQueue(address, m_mandatory_q_ptr);
398    } else if (request->ruby_request.type == RubyRequestType_Locked_RMW_Write) {
399        m_controller->unblock(address);
400    }
401
402    hitCallback(request, mach, data, success,
403                initialRequestTime, forwardRequestTime, firstResponseTime);
404}
405
406void
407Sequencer::readCallback(const Address& address, DataBlock& data)
408{
409    readCallback(address, GenericMachineType_NULL, data);
410}
411
412void
413Sequencer::readCallback(const Address& address,
414                        GenericMachineType mach,
415                        DataBlock& data)
416{
417    readCallback(address, mach, data, 0, 0, 0);
418}
419
420void
421Sequencer::readCallback(const Address& address,
422                        GenericMachineType mach,
423                        DataBlock& data,
424                        Time initialRequestTime,
425                        Time forwardRequestTime,
426                        Time firstResponseTime)
427{
428    assert(address == line_address(address));
429    assert(m_readRequestTable.count(line_address(address)));
430
431    RequestTable::iterator i = m_readRequestTable.find(address);
432    assert(i != m_readRequestTable.end());
433    SequencerRequest* request = i->second;
434
435    m_readRequestTable.erase(i);
436    markRemoved();
437
438    assert((request->ruby_request.type == RubyRequestType_LD) ||
439           (request->ruby_request.type == RubyRequestType_IFETCH));
440
441    hitCallback(request, mach, data, true,
442                initialRequestTime, forwardRequestTime, firstResponseTime);
443}
444
445void
446Sequencer::hitCallback(SequencerRequest* srequest,
447                       GenericMachineType mach,
448                       DataBlock& data,
449                       bool success,
450                       Time initialRequestTime,
451                       Time forwardRequestTime,
452                       Time firstResponseTime)
453{
454    const RubyRequest & ruby_request = srequest->ruby_request;
455    Address request_address(ruby_request.paddr);
456    Address request_line_address(ruby_request.paddr);
457    request_line_address.makeLineAddress();
458    RubyRequestType type = ruby_request.type;
459    Time issued_time = srequest->issue_time;
460
461    // Set this cache entry to the most recently used
462    if (type == RubyRequestType_IFETCH) {
463        if (m_instCache_ptr->isTagPresent(request_line_address))
464            m_instCache_ptr->setMRU(request_line_address);
465    } else {
466        if (m_dataCache_ptr->isTagPresent(request_line_address))
467            m_dataCache_ptr->setMRU(request_line_address);
468    }
469
470    assert(g_eventQueue_ptr->getTime() >= issued_time);
471    Time miss_latency = g_eventQueue_ptr->getTime() - issued_time;
472
473    // Profile the miss latency for all non-zero demand misses
474    if (miss_latency != 0) {
475        g_system_ptr->getProfiler()->missLatency(miss_latency, type, mach);
476
477        if (mach == GenericMachineType_L1Cache_wCC) {
478            g_system_ptr->getProfiler()->missLatencyWcc(issued_time,
479                                                   initialRequestTime,
480                                                   forwardRequestTime,
481                                                   firstResponseTime,
482                                                   g_eventQueue_ptr->getTime());
483        }
484
485        if (mach == GenericMachineType_Directory) {
486            g_system_ptr->getProfiler()->missLatencyDir(issued_time,
487                                                   initialRequestTime,
488                                                   forwardRequestTime,
489                                                   firstResponseTime,
490                                                   g_eventQueue_ptr->getTime());
491        }
492
493        DPRINTFR(ProtocolTrace, "%7s %3s %10s%20s %6s>%-6s %s %d cycles\n",
494            g_eventQueue_ptr->getTime(), m_version, "Seq",
495            success ? "Done" : "SC_Failed", "", "",
496            Address(ruby_request.paddr), miss_latency);
497    }
498#if 0
499    if (request.getPrefetch() == PrefetchBit_Yes) {
500        return; // Ignore the prefetch
501    }
502#endif
503
504    // update the data
505    if (ruby_request.data != NULL) {
506        if ((type == RubyRequestType_LD) ||
507            (type == RubyRequestType_IFETCH) ||
508            (type == RubyRequestType_RMW_Read) ||
509            (type == RubyRequestType_Locked_RMW_Read) ||
510            (type == RubyRequestType_Load_Linked)) {
511            memcpy(ruby_request.data,
512                   data.getData(request_address.getOffset(), ruby_request.len),
513                   ruby_request.len);
514        } else {
515            data.setData(ruby_request.data, request_address.getOffset(),
516                         ruby_request.len);
517        }
518    } else {
519        DPRINTF(MemoryAccess,
520                "WARNING.  Data not transfered from Ruby to M5 for type %s\n",
521                RubyRequestType_to_string(type));
522    }
523
524    // If using the RubyTester, update the RubyTester sender state's
525    // subBlock with the recieved data.  The tester will later access
526    // this state.
527    // Note: RubyPort will access it's sender state before the
528    // RubyTester.
529    if (m_usingRubyTester) {
530        RubyPort::SenderState *requestSenderState =
531            safe_cast<RubyPort::SenderState*>(ruby_request.pkt->senderState);
532        RubyTester::SenderState* testerSenderState =
533            safe_cast<RubyTester::SenderState*>(requestSenderState->saved);
534        testerSenderState->subBlock->mergeFrom(data);
535    }
536
537    ruby_hit_callback(ruby_request.pkt);
538    delete srequest;
539}
540
541// Returns true if the sequencer already has a load or store outstanding
542RequestStatus
543Sequencer::getRequestStatus(const RubyRequest& request)
544{
545    bool is_outstanding_store =
546        !!m_writeRequestTable.count(line_address(Address(request.paddr)));
547    bool is_outstanding_load =
548        !!m_readRequestTable.count(line_address(Address(request.paddr)));
549    if (is_outstanding_store) {
550        if ((request.type == RubyRequestType_LD) ||
551            (request.type == RubyRequestType_IFETCH) ||
552            (request.type == RubyRequestType_RMW_Read)) {
553            m_store_waiting_on_load_cycles++;
554        } else {
555            m_store_waiting_on_store_cycles++;
556        }
557        return RequestStatus_Aliased;
558    } else if (is_outstanding_load) {
559        if ((request.type == RubyRequestType_ST) ||
560            (request.type == RubyRequestType_RMW_Write)) {
561            m_load_waiting_on_store_cycles++;
562        } else {
563            m_load_waiting_on_load_cycles++;
564        }
565        return RequestStatus_Aliased;
566    }
567
568    if (m_outstanding_count >= m_max_outstanding_requests) {
569        return RequestStatus_BufferFull;
570    }
571
572    return RequestStatus_Ready;
573}
574
575bool
576Sequencer::empty() const
577{
578    return m_writeRequestTable.empty() && m_readRequestTable.empty();
579}
580
581RequestStatus
582Sequencer::makeRequest(const RubyRequest &request)
583{
584    assert(Address(request.paddr).getOffset() + request.len <=
585           RubySystem::getBlockSizeBytes());
586    RequestStatus status = getRequestStatus(request);
587    if (status != RequestStatus_Ready)
588        return status;
589
590    SequencerRequest *srequest =
591        new SequencerRequest(request, g_eventQueue_ptr->getTime());
592    bool found = insertRequest(srequest);
593    if (found) {
594        panic("Sequencer::makeRequest should never be called if the "
595              "request is already outstanding\n");
596        return RequestStatus_NULL;
597    }
598
599    issueRequest(request);
600
601    // TODO: issue hardware prefetches here
602    return RequestStatus_Issued;
603}
604
605void
606Sequencer::issueRequest(const RubyRequest& request)
607{
608    // TODO: get rid of CacheMsg, CacheRequestType, and
609    // AccessModeTYpe, & have SLICC use RubyRequest and subtypes
610    // natively
611    CacheRequestType ctype;
612    switch(request.type) {
613      case RubyRequestType_IFETCH:
614        ctype = CacheRequestType_IFETCH;
615        break;
616      case RubyRequestType_LD:
617        ctype = CacheRequestType_LD;
618        break;
619      case RubyRequestType_ST:
620      case RubyRequestType_RMW_Read:
621      case RubyRequestType_RMW_Write:
622      //
623      // x86 locked instructions are translated to store cache coherence
624      // requests because these requests should always be treated as read
625      // exclusive operations and should leverage any migratory sharing
626      // optimization built into the protocol.
627      //
628      case RubyRequestType_Locked_RMW_Read:
629      case RubyRequestType_Locked_RMW_Write:
630        ctype = CacheRequestType_ST;
631        break;
632      //
633      // Alpha LL/SC instructions need to be handled carefully by the cache
634      // coherence protocol to ensure they follow the proper semantics.  In
635      // particular, by identifying the operations as atomic, the protocol
636      // should understand that migratory sharing optimizations should not be
637      // performed (i.e. a load between the LL and SC should not steal away
638      // exclusive permission).
639      //
640      case RubyRequestType_Load_Linked:
641      case RubyRequestType_Store_Conditional:
642        ctype = CacheRequestType_ATOMIC;
643        break;
644      default:
645        assert(0);
646    }
647
648    AccessModeType amtype;
649    switch(request.access_mode){
650      case RubyAccessMode_User:
651        amtype = AccessModeType_UserMode;
652        break;
653      case RubyAccessMode_Supervisor:
654        amtype = AccessModeType_SupervisorMode;
655        break;
656      case RubyAccessMode_Device:
657        amtype = AccessModeType_UserMode;
658        break;
659      default:
660        assert(0);
661    }
662
663    Address line_addr(request.paddr);
664    line_addr.makeLineAddress();
665    CacheMsg *msg = new CacheMsg(line_addr, Address(request.paddr), ctype,
666        Address(request.pc), amtype, request.len, PrefetchBit_No,
667        request.proc_id);
668
669    DPRINTFR(ProtocolTrace, "%7s %3s %10s%20s %6s>%-6s %s %s\n",
670        g_eventQueue_ptr->getTime(), m_version, "Seq", "Begin", "", "",
671        Address(request.paddr), RubyRequestType_to_string(request.type));
672
673    Time latency = 0;  // initialzed to an null value
674
675    if (request.type == RubyRequestType_IFETCH)
676        latency = m_instCache_ptr->getLatency();
677    else
678        latency = m_dataCache_ptr->getLatency();
679
680    // Send the message to the cache controller
681    assert(latency > 0);
682
683    assert(m_mandatory_q_ptr != NULL);
684    m_mandatory_q_ptr->enqueue(msg, latency);
685}
686
687#if 0
688bool
689Sequencer::tryCacheAccess(const Address& addr, CacheRequestType type,
690                          AccessModeType access_mode,
691                          int size, DataBlock*& data_ptr)
692{
693    CacheMemory *cache =
694        (type == CacheRequestType_IFETCH) ? m_instCache_ptr : m_dataCache_ptr;
695
696    return cache->tryCacheAccess(line_address(addr), type, data_ptr);
697}
698#endif
699
700template <class KEY, class VALUE>
701std::ostream &
702operator<<(ostream &out, const m5::hash_map<KEY, VALUE> &map)
703{
704    typename m5::hash_map<KEY, VALUE>::const_iterator i = map.begin();
705    typename m5::hash_map<KEY, VALUE>::const_iterator end = map.end();
706
707    out << "[";
708    for (; i != end; ++i)
709        out << " " << i->first << "=" << i->second;
710    out << " ]";
711
712    return out;
713}
714
715void
716Sequencer::print(ostream& out) const
717{
718    out << "[Sequencer: " << m_version
719        << ", outstanding requests: " << m_outstanding_count
720        << ", read request table: " << m_readRequestTable
721        << ", write request table: " << m_writeRequestTable
722        << "]";
723}
724
725// this can be called from setState whenever coherence permissions are
726// upgraded when invoked, coherence violations will be checked for the
727// given block
728void
729Sequencer::checkCoherence(const Address& addr)
730{
731#ifdef CHECK_COHERENCE
732    g_system_ptr->checkGlobalCoherenceInvariant(addr);
733#endif
734}
735