Sequencer.cc revision 7560
1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include "base/str.hh" 30#include "cpu/rubytest/RubyTester.hh" 31#include "mem/protocol/CacheMsg.hh" 32#include "mem/protocol/Protocol.hh" 33#include "mem/protocol/Protocol.hh" 34#include "mem/ruby/buffers/MessageBuffer.hh" 35#include "mem/ruby/common/Global.hh" 36#include "mem/ruby/common/SubBlock.hh" 37#include "mem/ruby/libruby.hh" 38#include "mem/ruby/profiler/Profiler.hh" 39#include "mem/ruby/recorder/Tracer.hh" 40#include "mem/ruby/slicc_interface/AbstractController.hh" 41#include "mem/ruby/system/CacheMemory.hh" 42#include "mem/ruby/system/Sequencer.hh" 43#include "mem/ruby/system/System.hh" 44#include "mem/packet.hh" 45#include "params/RubySequencer.hh" 46 47using namespace std; 48 49Sequencer * 50RubySequencerParams::create() 51{ 52 return new Sequencer(this); 53} 54 55Sequencer::Sequencer(const Params *p) 56 : RubyPort(p), deadlockCheckEvent(this) 57{ 58 m_store_waiting_on_load_cycles = 0; 59 m_store_waiting_on_store_cycles = 0; 60 m_load_waiting_on_store_cycles = 0; 61 m_load_waiting_on_load_cycles = 0; 62 63 m_outstanding_count = 0; 64 65 m_max_outstanding_requests = 0; 66 m_deadlock_threshold = 0; 67 m_instCache_ptr = NULL; 68 m_dataCache_ptr = NULL; 69 70 m_instCache_ptr = p->icache; 71 m_dataCache_ptr = p->dcache; 72 m_max_outstanding_requests = p->max_outstanding_requests; 73 m_deadlock_threshold = p->deadlock_threshold; 74 m_usingRubyTester = p->using_ruby_tester; 75 76 assert(m_max_outstanding_requests > 0); 77 assert(m_deadlock_threshold > 0); 78 assert(m_instCache_ptr != NULL); 79 assert(m_dataCache_ptr != NULL); 80} 81 82Sequencer::~Sequencer() 83{ 84} 85 86void 87Sequencer::wakeup() 88{ 89 // Check for deadlock of any of the requests 90 Time current_time = g_eventQueue_ptr->getTime(); 91 92 // Check across all outstanding requests 93 int total_outstanding = 0; 94 95 RequestTable::iterator read = m_readRequestTable.begin(); 96 RequestTable::iterator read_end = m_readRequestTable.end(); 97 for (; read != read_end; ++read) { 98 SequencerRequest* request = read->second; 99 if (current_time - request->issue_time < m_deadlock_threshold) 100 continue; 101 102 WARN_MSG("Possible Deadlock detected"); 103 WARN_EXPR(m_version); 104 WARN_EXPR(request->ruby_request.paddr); 105 WARN_EXPR(m_readRequestTable.size()); 106 WARN_EXPR(current_time); 107 WARN_EXPR(request->issue_time); 108 WARN_EXPR(current_time - request->issue_time); 109 ERROR_MSG("Aborting"); 110 } 111 112 RequestTable::iterator write = m_writeRequestTable.begin(); 113 RequestTable::iterator write_end = m_writeRequestTable.end(); 114 for (; write != write_end; ++write) { 115 SequencerRequest* request = write->second; 116 if (current_time - request->issue_time < m_deadlock_threshold) 117 continue; 118 119 WARN_MSG("Possible Deadlock detected"); 120 WARN_EXPR(m_version); 121 WARN_EXPR(request->ruby_request.paddr); 122 WARN_EXPR(current_time); 123 WARN_EXPR(request->issue_time); 124 WARN_EXPR(current_time - request->issue_time); 125 WARN_EXPR(m_writeRequestTable.size()); 126 ERROR_MSG("Aborting"); 127 } 128 129 total_outstanding += m_writeRequestTable.size(); 130 total_outstanding += m_readRequestTable.size(); 131 132 assert(m_outstanding_count == total_outstanding); 133 134 if (m_outstanding_count > 0) { 135 // If there are still outstanding requests, keep checking 136 schedule(deadlockCheckEvent, 137 m_deadlock_threshold * g_eventQueue_ptr->getClock() + 138 curTick); 139 } 140} 141 142void 143Sequencer::printStats(ostream & out) const 144{ 145 out << "Sequencer: " << m_name << endl 146 << " store_waiting_on_load_cycles: " 147 << m_store_waiting_on_load_cycles << endl 148 << " store_waiting_on_store_cycles: " 149 << m_store_waiting_on_store_cycles << endl 150 << " load_waiting_on_load_cycles: " 151 << m_load_waiting_on_load_cycles << endl 152 << " load_waiting_on_store_cycles: " 153 << m_load_waiting_on_store_cycles << endl; 154} 155 156void 157Sequencer::printProgress(ostream& out) const 158{ 159#if 0 160 int total_demand = 0; 161 out << "Sequencer Stats Version " << m_version << endl; 162 out << "Current time = " << g_eventQueue_ptr->getTime() << endl; 163 out << "---------------" << endl; 164 out << "outstanding requests" << endl; 165 166 out << "proc " << m_Read 167 << " version Requests = " << m_readRequestTable.size() << endl; 168 169 // print the request table 170 RequestTable::iterator read = m_readRequestTable.begin(); 171 RequestTable::iterator read_end = m_readRequestTable.end(); 172 for (; read != read_end; ++read) { 173 SequencerRequest* request = read->second; 174 out << "\tRequest[ " << i << " ] = " << request->type 175 << " Address " << rkeys[i] 176 << " Posted " << request->issue_time 177 << " PF " << PrefetchBit_No << endl; 178 total_demand++; 179 } 180 181 out << "proc " << m_version 182 << " Write Requests = " << m_writeRequestTable.size << endl; 183 184 // print the request table 185 RequestTable::iterator write = m_writeRequestTable.begin(); 186 RequestTable::iterator write_end = m_writeRequestTable.end(); 187 for (; write != write_end; ++write) { 188 SequencerRequest* request = write->second; 189 out << "\tRequest[ " << i << " ] = " << request.getType() 190 << " Address " << wkeys[i] 191 << " Posted " << request.getTime() 192 << " PF " << request.getPrefetch() << endl; 193 if (request.getPrefetch() == PrefetchBit_No) { 194 total_demand++; 195 } 196 } 197 198 out << endl; 199 200 out << "Total Number Outstanding: " << m_outstanding_count << endl 201 << "Total Number Demand : " << total_demand << endl 202 << "Total Number Prefetches : " << m_outstanding_count - total_demand 203 << endl << endl << endl; 204#endif 205} 206 207void 208Sequencer::printConfig(ostream& out) const 209{ 210 out << "Seqeuncer config: " << m_name << endl 211 << " controller: " << m_controller->getName() << endl 212 << " version: " << m_version << endl 213 << " max_outstanding_requests: " << m_max_outstanding_requests << endl 214 << " deadlock_threshold: " << m_deadlock_threshold << endl; 215} 216 217// Insert the request on the correct request table. Return true if 218// the entry was already present. 219bool 220Sequencer::insertRequest(SequencerRequest* request) 221{ 222 int total_outstanding = 223 m_writeRequestTable.size() + m_readRequestTable.size(); 224 225 assert(m_outstanding_count == total_outstanding); 226 227 // See if we should schedule a deadlock check 228 if (deadlockCheckEvent.scheduled() == false) { 229 schedule(deadlockCheckEvent, m_deadlock_threshold + curTick); 230 } 231 232 Address line_addr(request->ruby_request.paddr); 233 line_addr.makeLineAddress(); 234 if ((request->ruby_request.type == RubyRequestType_ST) || 235 (request->ruby_request.type == RubyRequestType_RMW_Read) || 236 (request->ruby_request.type == RubyRequestType_RMW_Write) || 237 (request->ruby_request.type == RubyRequestType_Locked_Read) || 238 (request->ruby_request.type == RubyRequestType_Locked_Write)) { 239 pair<RequestTable::iterator, bool> r = 240 m_writeRequestTable.insert(RequestTable::value_type(line_addr, 0)); 241 bool success = r.second; 242 RequestTable::iterator i = r.first; 243 if (!success) { 244 i->second = request; 245 // return true; 246 247 // drh5: isn't this an error? do you lose the initial request? 248 assert(0); 249 } 250 i->second = request; 251 m_outstanding_count++; 252 } else { 253 pair<RequestTable::iterator, bool> r = 254 m_readRequestTable.insert(RequestTable::value_type(line_addr, 0)); 255 bool success = r.second; 256 RequestTable::iterator i = r.first; 257 if (!success) { 258 i->second = request; 259 // return true; 260 261 // drh5: isn't this an error? do you lose the initial request? 262 assert(0); 263 } 264 i->second = request; 265 m_outstanding_count++; 266 } 267 268 g_system_ptr->getProfiler()->sequencerRequests(m_outstanding_count); 269 270 total_outstanding = m_writeRequestTable.size() + m_readRequestTable.size(); 271 assert(m_outstanding_count == total_outstanding); 272 273 return false; 274} 275 276void 277Sequencer::markRemoved() 278{ 279 m_outstanding_count--; 280 assert(m_outstanding_count == 281 m_writeRequestTable.size() + m_readRequestTable.size()); 282} 283 284void 285Sequencer::removeRequest(SequencerRequest* srequest) 286{ 287 assert(m_outstanding_count == 288 m_writeRequestTable.size() + m_readRequestTable.size()); 289 290 const RubyRequest & ruby_request = srequest->ruby_request; 291 Address line_addr(ruby_request.paddr); 292 line_addr.makeLineAddress(); 293 if ((ruby_request.type == RubyRequestType_ST) || 294 (ruby_request.type == RubyRequestType_RMW_Read) || 295 (ruby_request.type == RubyRequestType_RMW_Write) || 296 (ruby_request.type == RubyRequestType_Locked_Read) || 297 (ruby_request.type == RubyRequestType_Locked_Write)) { 298 m_writeRequestTable.erase(line_addr); 299 } else { 300 m_readRequestTable.erase(line_addr); 301 } 302 303 markRemoved(); 304} 305 306bool 307Sequencer::handleLlsc(const Address& address, SequencerRequest* request) 308{ 309 // 310 // The success flag indicates whether the LLSC operation was successful. 311 // LL ops will always succeed, but SC may fail if the cache line is no 312 // longer locked. 313 // 314 bool success = true; 315 if (request->ruby_request.type == RubyRequestType_Locked_Write) { 316 if (!m_dataCache_ptr->isLocked(address, m_version)) { 317 // 318 // For failed SC requests, indicate the failure to the cpu by 319 // setting the extra data to zero. 320 // 321 request->ruby_request.pkt->req->setExtraData(0); 322 success = false; 323 } else { 324 // 325 // For successful SC requests, indicate the success to the cpu by 326 // setting the extra data to one. 327 // 328 request->ruby_request.pkt->req->setExtraData(1); 329 } 330 // 331 // Independent of success, all SC operations must clear the lock 332 // 333 m_dataCache_ptr->clearLocked(address); 334 } else if (request->ruby_request.type == RubyRequestType_Locked_Read) { 335 // 336 // Note: To fully follow Alpha LLSC semantics, should the LL clear any 337 // previously locked cache lines? 338 // 339 m_dataCache_ptr->setLocked(address, m_version); 340 } else if (m_dataCache_ptr->isLocked(address, m_version)) { 341 // 342 // Normal writes should clear the locked address 343 // 344 m_dataCache_ptr->clearLocked(address); 345 } 346 return success; 347} 348 349void 350Sequencer::writeCallback(const Address& address, DataBlock& data) 351{ 352 writeCallback(address, GenericMachineType_NULL, data); 353} 354 355void 356Sequencer::writeCallback(const Address& address, 357 GenericMachineType mach, 358 DataBlock& data) 359{ 360 assert(address == line_address(address)); 361 assert(m_writeRequestTable.count(line_address(address))); 362 363 RequestTable::iterator i = m_writeRequestTable.find(address); 364 assert(i != m_writeRequestTable.end()); 365 SequencerRequest* request = i->second; 366 367 m_writeRequestTable.erase(i); 368 markRemoved(); 369 370 assert((request->ruby_request.type == RubyRequestType_ST) || 371 (request->ruby_request.type == RubyRequestType_RMW_Read) || 372 (request->ruby_request.type == RubyRequestType_RMW_Write) || 373 (request->ruby_request.type == RubyRequestType_Locked_Read) || 374 (request->ruby_request.type == RubyRequestType_Locked_Write)); 375 376 // 377 // For Alpha, properly handle LL, SC, and write requests with respect to 378 // locked cache blocks. 379 // 380 bool success = handleLlsc(address, request); 381 382 if (request->ruby_request.type == RubyRequestType_RMW_Read) { 383 m_controller->blockOnQueue(address, m_mandatory_q_ptr); 384 } else if (request->ruby_request.type == RubyRequestType_RMW_Write) { 385 m_controller->unblock(address); 386 } 387 388 hitCallback(request, mach, data, success); 389} 390 391void 392Sequencer::readCallback(const Address& address, DataBlock& data) 393{ 394 readCallback(address, GenericMachineType_NULL, data); 395} 396 397void 398Sequencer::readCallback(const Address& address, 399 GenericMachineType mach, 400 DataBlock& data) 401{ 402 assert(address == line_address(address)); 403 assert(m_readRequestTable.count(line_address(address))); 404 405 RequestTable::iterator i = m_readRequestTable.find(address); 406 assert(i != m_readRequestTable.end()); 407 SequencerRequest* request = i->second; 408 409 m_readRequestTable.erase(i); 410 markRemoved(); 411 412 assert((request->ruby_request.type == RubyRequestType_LD) || 413 (request->ruby_request.type == RubyRequestType_RMW_Read) || 414 (request->ruby_request.type == RubyRequestType_IFETCH)); 415 416 hitCallback(request, mach, data, true); 417} 418 419void 420Sequencer::hitCallback(SequencerRequest* srequest, 421 GenericMachineType mach, 422 DataBlock& data, 423 bool success) 424{ 425 const RubyRequest & ruby_request = srequest->ruby_request; 426 Address request_address(ruby_request.paddr); 427 Address request_line_address(ruby_request.paddr); 428 request_line_address.makeLineAddress(); 429 RubyRequestType type = ruby_request.type; 430 Time issued_time = srequest->issue_time; 431 432 // Set this cache entry to the most recently used 433 if (type == RubyRequestType_IFETCH) { 434 if (m_instCache_ptr->isTagPresent(request_line_address)) 435 m_instCache_ptr->setMRU(request_line_address); 436 } else { 437 if (m_dataCache_ptr->isTagPresent(request_line_address)) 438 m_dataCache_ptr->setMRU(request_line_address); 439 } 440 441 assert(g_eventQueue_ptr->getTime() >= issued_time); 442 Time miss_latency = g_eventQueue_ptr->getTime() - issued_time; 443 444 // Profile the miss latency for all non-zero demand misses 445 if (miss_latency != 0) { 446 g_system_ptr->getProfiler()->missLatency(miss_latency, type, mach); 447 448 if (Debug::getProtocolTrace()) { 449 if (success) { 450 g_system_ptr->getProfiler()-> 451 profileTransition("Seq", m_version, 452 Address(ruby_request.paddr), "", "Done", "", 453 csprintf("%d cycles", miss_latency)); 454 } else { 455 g_system_ptr->getProfiler()-> 456 profileTransition("Seq", m_version, 457 Address(ruby_request.paddr), "", "SC_Failed", "", 458 csprintf("%d cycles", miss_latency)); 459 } 460 } 461 } 462#if 0 463 if (request.getPrefetch() == PrefetchBit_Yes) { 464 return; // Ignore the prefetch 465 } 466#endif 467 468 // update the data 469 if (ruby_request.data != NULL) { 470 if ((type == RubyRequestType_LD) || 471 (type == RubyRequestType_IFETCH) || 472 (type == RubyRequestType_RMW_Read) || 473 (type == RubyRequestType_Locked_Read)) { 474 475 memcpy(ruby_request.data, 476 data.getData(request_address.getOffset(), ruby_request.len), 477 ruby_request.len); 478 } else { 479 data.setData(ruby_request.data, request_address.getOffset(), 480 ruby_request.len); 481 } 482 } else { 483 DPRINTF(MemoryAccess, 484 "WARNING. Data not transfered from Ruby to M5 for type %s\n", 485 RubyRequestType_to_string(type)); 486 } 487 488 // If using the RubyTester, update the RubyTester sender state's 489 // subBlock with the recieved data. The tester will later access 490 // this state. 491 // Note: RubyPort will access it's sender state before the 492 // RubyTester. 493 if (m_usingRubyTester) { 494 RubyPort::SenderState *requestSenderState = 495 safe_cast<RubyPort::SenderState*>(ruby_request.pkt->senderState); 496 RubyTester::SenderState* testerSenderState = 497 safe_cast<RubyTester::SenderState*>(requestSenderState->saved); 498 testerSenderState->subBlock->mergeFrom(data); 499 } 500 501 ruby_hit_callback(ruby_request.pkt); 502 delete srequest; 503} 504 505// Returns true if the sequencer already has a load or store outstanding 506RequestStatus 507Sequencer::getRequestStatus(const RubyRequest& request) 508{ 509 bool is_outstanding_store = 510 !!m_writeRequestTable.count(line_address(Address(request.paddr))); 511 bool is_outstanding_load = 512 !!m_readRequestTable.count(line_address(Address(request.paddr))); 513 if (is_outstanding_store) { 514 if ((request.type == RubyRequestType_LD) || 515 (request.type == RubyRequestType_IFETCH) || 516 (request.type == RubyRequestType_RMW_Read)) { 517 m_store_waiting_on_load_cycles++; 518 } else { 519 m_store_waiting_on_store_cycles++; 520 } 521 return RequestStatus_Aliased; 522 } else if (is_outstanding_load) { 523 if ((request.type == RubyRequestType_ST) || 524 (request.type == RubyRequestType_RMW_Write)) { 525 m_load_waiting_on_store_cycles++; 526 } else { 527 m_load_waiting_on_load_cycles++; 528 } 529 return RequestStatus_Aliased; 530 } 531 532 if (m_outstanding_count >= m_max_outstanding_requests) { 533 return RequestStatus_BufferFull; 534 } 535 536 return RequestStatus_Ready; 537} 538 539bool 540Sequencer::empty() const 541{ 542 return m_writeRequestTable.empty() && m_readRequestTable.empty(); 543} 544 545RequestStatus 546Sequencer::makeRequest(const RubyRequest &request) 547{ 548 assert(Address(request.paddr).getOffset() + request.len <= 549 RubySystem::getBlockSizeBytes()); 550 RequestStatus status = getRequestStatus(request); 551 if (status != RequestStatus_Ready) 552 return status; 553 554 SequencerRequest *srequest = 555 new SequencerRequest(request, g_eventQueue_ptr->getTime()); 556 bool found = insertRequest(srequest); 557 if (found) { 558 panic("Sequencer::makeRequest should never be called if the " 559 "request is already outstanding\n"); 560 return RequestStatus_NULL; 561 } 562 563 issueRequest(request); 564 565 // TODO: issue hardware prefetches here 566 return RequestStatus_Issued; 567} 568 569void 570Sequencer::issueRequest(const RubyRequest& request) 571{ 572 // TODO: get rid of CacheMsg, CacheRequestType, and 573 // AccessModeTYpe, & have SLICC use RubyRequest and subtypes 574 // natively 575 CacheRequestType ctype; 576 switch(request.type) { 577 case RubyRequestType_IFETCH: 578 ctype = CacheRequestType_IFETCH; 579 break; 580 case RubyRequestType_LD: 581 ctype = CacheRequestType_LD; 582 break; 583 case RubyRequestType_ST: 584 ctype = CacheRequestType_ST; 585 break; 586 case RubyRequestType_Locked_Read: 587 case RubyRequestType_Locked_Write: 588 ctype = CacheRequestType_ATOMIC; 589 break; 590 case RubyRequestType_RMW_Read: 591 ctype = CacheRequestType_ATOMIC; 592 break; 593 case RubyRequestType_RMW_Write: 594 ctype = CacheRequestType_ATOMIC; 595 break; 596 default: 597 assert(0); 598 } 599 600 AccessModeType amtype; 601 switch(request.access_mode){ 602 case RubyAccessMode_User: 603 amtype = AccessModeType_UserMode; 604 break; 605 case RubyAccessMode_Supervisor: 606 amtype = AccessModeType_SupervisorMode; 607 break; 608 case RubyAccessMode_Device: 609 amtype = AccessModeType_UserMode; 610 break; 611 default: 612 assert(0); 613 } 614 615 Address line_addr(request.paddr); 616 line_addr.makeLineAddress(); 617 CacheMsg *msg = new CacheMsg(line_addr, Address(request.paddr), ctype, 618 Address(request.pc), amtype, request.len, PrefetchBit_No, 619 request.proc_id); 620 621 if (Debug::getProtocolTrace()) { 622 g_system_ptr->getProfiler()-> 623 profileTransition("Seq", m_version, Address(request.paddr), 624 "", "Begin", "", 625 RubyRequestType_to_string(request.type)); 626 } 627 628 if (g_system_ptr->getTracer()->traceEnabled()) { 629 g_system_ptr->getTracer()-> 630 traceRequest(this, line_addr, Address(request.pc), 631 request.type, g_eventQueue_ptr->getTime()); 632 } 633 634 Time latency = 0; // initialzed to an null value 635 636 if (request.type == RubyRequestType_IFETCH) 637 latency = m_instCache_ptr->getLatency(); 638 else 639 latency = m_dataCache_ptr->getLatency(); 640 641 // Send the message to the cache controller 642 assert(latency > 0); 643 644 assert(m_mandatory_q_ptr != NULL); 645 m_mandatory_q_ptr->enqueue(msg, latency); 646} 647 648#if 0 649bool 650Sequencer::tryCacheAccess(const Address& addr, CacheRequestType type, 651 AccessModeType access_mode, 652 int size, DataBlock*& data_ptr) 653{ 654 CacheMemory *cache = 655 (type == CacheRequestType_IFETCH) ? m_instCache_ptr : m_dataCache_ptr; 656 657 return cache->tryCacheAccess(line_address(addr), type, data_ptr); 658} 659#endif 660 661template <class KEY, class VALUE> 662std::ostream & 663operator<<(ostream &out, const m5::hash_map<KEY, VALUE> &map) 664{ 665 typename m5::hash_map<KEY, VALUE>::const_iterator i = map.begin(); 666 typename m5::hash_map<KEY, VALUE>::const_iterator end = map.end(); 667 668 out << "["; 669 for (; i != end; ++i) 670 out << " " << i->first << "=" << i->second; 671 out << " ]"; 672 673 return out; 674} 675 676void 677Sequencer::print(ostream& out) const 678{ 679 out << "[Sequencer: " << m_version 680 << ", outstanding requests: " << m_outstanding_count 681 << ", read request table: " << m_readRequestTable 682 << ", write request table: " << m_writeRequestTable 683 << "]"; 684} 685 686// this can be called from setState whenever coherence permissions are 687// upgraded when invoked, coherence violations will be checked for the 688// given block 689void 690Sequencer::checkCoherence(const Address& addr) 691{ 692#ifdef CHECK_COHERENCE 693 g_system_ptr->checkGlobalCoherenceInvariant(addr); 694#endif 695} 696