Sequencer.cc revision 7055:4e24742201d7 
1/*
2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "cpu/rubytest/RubyTester.hh"
30#include "mem/gems_common/Map.hh"
31#include "mem/protocol/CacheMsg.hh"
32#include "mem/protocol/Protocol.hh"
33#include "mem/protocol/Protocol.hh"
34#include "mem/ruby/buffers/MessageBuffer.hh"
35#include "mem/ruby/common/Global.hh"
36#include "mem/ruby/common/SubBlock.hh"
37#include "mem/ruby/libruby.hh"
38#include "mem/ruby/profiler/Profiler.hh"
39#include "mem/ruby/recorder/Tracer.hh"
40#include "mem/ruby/slicc_interface/AbstractController.hh"
41#include "mem/ruby/system/CacheMemory.hh"
42#include "mem/ruby/system/Sequencer.hh"
43#include "mem/ruby/system/System.hh"
44#include "params/RubySequencer.hh"
45
46using namespace std;
47
48Sequencer *
49RubySequencerParams::create()
50{
51    return new Sequencer(this);
52}
53
54Sequencer::Sequencer(const Params *p)
55    : RubyPort(p), deadlockCheckEvent(this)
56{
57    m_store_waiting_on_load_cycles = 0;
58    m_store_waiting_on_store_cycles = 0;
59    m_load_waiting_on_store_cycles = 0;
60    m_load_waiting_on_load_cycles = 0;
61
62    m_outstanding_count = 0;
63
64    m_max_outstanding_requests = 0;
65    m_deadlock_threshold = 0;
66    m_instCache_ptr = NULL;
67    m_dataCache_ptr = NULL;
68
69    m_instCache_ptr = p->icache;
70    m_dataCache_ptr = p->dcache;
71    m_max_outstanding_requests = p->max_outstanding_requests;
72    m_deadlock_threshold = p->deadlock_threshold;
73    m_usingRubyTester = p->using_ruby_tester;
74
75    assert(m_max_outstanding_requests > 0);
76    assert(m_deadlock_threshold > 0);
77    assert(m_instCache_ptr != NULL);
78    assert(m_dataCache_ptr != NULL);
79}
80
81Sequencer::~Sequencer()
82{
83}
84
85void
86Sequencer::wakeup()
87{
88    // Check for deadlock of any of the requests
89    Time current_time = g_eventQueue_ptr->getTime();
90
91    // Check across all outstanding requests
92    int total_outstanding = 0;
93
94    Vector<Address> keys = m_readRequestTable.keys();
95    for (int i = 0; i < keys.size(); i++) {
96        SequencerRequest* request = m_readRequestTable.lookup(keys[i]);
97        if (current_time - request->issue_time >= m_deadlock_threshold) {
98            WARN_MSG("Possible Deadlock detected");
99            WARN_EXPR(request);
100            WARN_EXPR(m_version);
101            WARN_EXPR(request->ruby_request.paddr);
102            WARN_EXPR(keys.size());
103            WARN_EXPR(current_time);
104            WARN_EXPR(request->issue_time);
105            WARN_EXPR(current_time - request->issue_time);
106            ERROR_MSG("Aborting");
107        }
108    }
109
110    keys = m_writeRequestTable.keys();
111    for (int i = 0; i < keys.size(); i++) {
112        SequencerRequest* request = m_writeRequestTable.lookup(keys[i]);
113        if (current_time - request->issue_time >= m_deadlock_threshold) {
114            WARN_MSG("Possible Deadlock detected");
115            WARN_EXPR(request);
116            WARN_EXPR(m_version);
117            WARN_EXPR(current_time);
118            WARN_EXPR(request->issue_time);
119            WARN_EXPR(current_time - request->issue_time);
120            WARN_EXPR(keys.size());
121            ERROR_MSG("Aborting");
122        }
123    }
124
125    total_outstanding += m_writeRequestTable.size();
126    total_outstanding += m_readRequestTable.size();
127
128    assert(m_outstanding_count == total_outstanding);
129
130    if (m_outstanding_count > 0) {
131        // If there are still outstanding requests, keep checking
132        schedule(deadlockCheckEvent,
133                 m_deadlock_threshold * g_eventQueue_ptr->getClock() +
134                 curTick);
135    }
136}
137
138void
139Sequencer::printStats(ostream & out) const
140{
141    out << "Sequencer: " << m_name << endl
142        << "  store_waiting_on_load_cycles: "
143        << m_store_waiting_on_load_cycles << endl
144        << "  store_waiting_on_store_cycles: "
145        << m_store_waiting_on_store_cycles << endl
146        << "  load_waiting_on_load_cycles: "
147        << m_load_waiting_on_load_cycles << endl
148        << "  load_waiting_on_store_cycles: "
149        << m_load_waiting_on_store_cycles << endl;
150}
151
152void
153Sequencer::printProgress(ostream& out) const
154{
155#if 0
156    int total_demand = 0;
157    out << "Sequencer Stats Version " << m_version << endl;
158    out << "Current time = " << g_eventQueue_ptr->getTime() << endl;
159    out << "---------------" << endl;
160    out << "outstanding requests" << endl;
161
162    Vector<Address> rkeys = m_readRequestTable.keys();
163    int read_size = rkeys.size();
164    out << "proc " << m_version << " Read Requests = " << read_size << endl;
165
166    // print the request table
167    for (int i = 0; i < read_size; ++i) {
168        SequencerRequest *request = m_readRequestTable.lookup(rkeys[i]);
169        out << "\tRequest[ " << i << " ] = " << request->type
170            << " Address " << rkeys[i]
171            << " Posted " << request->issue_time
172            << " PF " << PrefetchBit_No << endl;
173        total_demand++;
174    }
175
176    Vector<Address> wkeys = m_writeRequestTable.keys();
177    int write_size = wkeys.size();
178    out << "proc " << m_version << " Write Requests = " << write_size << endl;
179
180    // print the request table
181    for (int i = 0; i < write_size; ++i){
182        CacheMsg &request = m_writeRequestTable.lookup(wkeys[i]);
183        out << "\tRequest[ " << i << " ] = " << request.getType()
184            << " Address " << wkeys[i]
185            << " Posted " << request.getTime()
186            << " PF " << request.getPrefetch() << endl;
187        if (request.getPrefetch() == PrefetchBit_No) {
188            total_demand++;
189        }
190    }
191
192    out << endl;
193
194    out << "Total Number Outstanding: " << m_outstanding_count << endl
195        << "Total Number Demand     : " << total_demand << endl
196        << "Total Number Prefetches : " << m_outstanding_count - total_demand
197        << endl << endl << endl;
198#endif
199}
200
201void
202Sequencer::printConfig(ostream& out) const
203{
204    out << "Seqeuncer config: " << m_name << endl
205        << "  controller: " << m_controller->getName() << endl
206        << "  version: " << m_version << endl
207        << "  max_outstanding_requests: " << m_max_outstanding_requests << endl
208        << "  deadlock_threshold: " << m_deadlock_threshold << endl;
209}
210
211// Insert the request on the correct request table.  Return true if
212// the entry was already present.
213bool
214Sequencer::insertRequest(SequencerRequest* request)
215{
216    int total_outstanding =
217        m_writeRequestTable.size() + m_readRequestTable.size();
218
219    assert(m_outstanding_count == total_outstanding);
220
221    // See if we should schedule a deadlock check
222    if (deadlockCheckEvent.scheduled() == false) {
223        schedule(deadlockCheckEvent, m_deadlock_threshold + curTick);
224    }
225
226    Address line_addr(request->ruby_request.paddr);
227    line_addr.makeLineAddress();
228    if ((request->ruby_request.type == RubyRequestType_ST) ||
229        (request->ruby_request.type == RubyRequestType_RMW_Read) ||
230        (request->ruby_request.type == RubyRequestType_RMW_Write) ||
231        (request->ruby_request.type == RubyRequestType_Locked_Read) ||
232        (request->ruby_request.type == RubyRequestType_Locked_Write)) {
233        if (m_writeRequestTable.exist(line_addr)) {
234            m_writeRequestTable.lookup(line_addr) = request;
235            // return true;
236
237            // drh5: isn't this an error?  do you lose the initial request?
238            assert(0);
239        }
240        m_writeRequestTable.allocate(line_addr);
241        m_writeRequestTable.lookup(line_addr) = request;
242        m_outstanding_count++;
243    } else {
244        if (m_readRequestTable.exist(line_addr)) {
245            m_readRequestTable.lookup(line_addr) = request;
246            // return true;
247
248            // drh5: isn't this an error?  do you lose the initial request?
249            assert(0);
250        }
251        m_readRequestTable.allocate(line_addr);
252        m_readRequestTable.lookup(line_addr) = request;
253        m_outstanding_count++;
254    }
255
256    g_system_ptr->getProfiler()->sequencerRequests(m_outstanding_count);
257
258    total_outstanding = m_writeRequestTable.size() + m_readRequestTable.size();
259    assert(m_outstanding_count == total_outstanding);
260
261    return false;
262}
263
264void
265Sequencer::removeRequest(SequencerRequest* srequest)
266{
267    assert(m_outstanding_count ==
268           m_writeRequestTable.size() + m_readRequestTable.size());
269
270    const RubyRequest & ruby_request = srequest->ruby_request;
271    Address line_addr(ruby_request.paddr);
272    line_addr.makeLineAddress();
273    if ((ruby_request.type == RubyRequestType_ST) ||
274        (ruby_request.type == RubyRequestType_RMW_Read) ||
275        (ruby_request.type == RubyRequestType_RMW_Write) ||
276        (ruby_request.type == RubyRequestType_Locked_Read) ||
277        (ruby_request.type == RubyRequestType_Locked_Write)) {
278        m_writeRequestTable.deallocate(line_addr);
279    } else {
280        m_readRequestTable.deallocate(line_addr);
281    }
282    m_outstanding_count--;
283
284    assert(m_outstanding_count == m_writeRequestTable.size() + m_readRequestTable.size());
285}
286
287void
288Sequencer::writeCallback(const Address& address, DataBlock& data)
289{
290    assert(address == line_address(address));
291    assert(m_writeRequestTable.exist(line_address(address)));
292
293    SequencerRequest* request = m_writeRequestTable.lookup(address);
294
295    removeRequest(request);
296
297    assert((request->ruby_request.type == RubyRequestType_ST) ||
298           (request->ruby_request.type == RubyRequestType_RMW_Read) ||
299           (request->ruby_request.type == RubyRequestType_RMW_Write) ||
300           (request->ruby_request.type == RubyRequestType_Locked_Read) ||
301           (request->ruby_request.type == RubyRequestType_Locked_Write));
302
303    if (request->ruby_request.type == RubyRequestType_Locked_Read) {
304        m_dataCache_ptr->setLocked(address, m_version);
305    } else if (request->ruby_request.type == RubyRequestType_RMW_Read) {
306        m_controller->blockOnQueue(address, m_mandatory_q_ptr);
307    } else if (request->ruby_request.type == RubyRequestType_RMW_Write) {
308        m_controller->unblock(address);
309    }
310
311    hitCallback(request, data);
312}
313
314void
315Sequencer::readCallback(const Address& address, DataBlock& data)
316{
317    assert(address == line_address(address));
318    assert(m_readRequestTable.exist(line_address(address)));
319
320    SequencerRequest* request = m_readRequestTable.lookup(address);
321    removeRequest(request);
322
323    assert((request->ruby_request.type == RubyRequestType_LD) ||
324           (request->ruby_request.type == RubyRequestType_RMW_Read) ||
325           (request->ruby_request.type == RubyRequestType_IFETCH));
326
327    hitCallback(request, data);
328}
329
330void
331Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data)
332{
333    const RubyRequest & ruby_request = srequest->ruby_request;
334    Address request_address(ruby_request.paddr);
335    Address request_line_address(ruby_request.paddr);
336    request_line_address.makeLineAddress();
337    RubyRequestType type = ruby_request.type;
338    Time issued_time = srequest->issue_time;
339
340    // Set this cache entry to the most recently used
341    if (type == RubyRequestType_IFETCH) {
342        if (m_instCache_ptr->isTagPresent(request_line_address))
343            m_instCache_ptr->setMRU(request_line_address);
344    } else {
345        if (m_dataCache_ptr->isTagPresent(request_line_address))
346            m_dataCache_ptr->setMRU(request_line_address);
347    }
348
349    assert(g_eventQueue_ptr->getTime() >= issued_time);
350    Time miss_latency = g_eventQueue_ptr->getTime() - issued_time;
351
352    // Profile the miss latency for all non-zero demand misses
353    if (miss_latency != 0) {
354        g_system_ptr->getProfiler()->missLatency(miss_latency, type);
355
356        if (Debug::getProtocolTrace()) {
357            g_system_ptr->getProfiler()->
358                profileTransition("Seq", m_version,
359                                  Address(ruby_request.paddr), "", "Done", "",
360                                  csprintf("%d cycles", miss_latency));
361        }
362    }
363#if 0
364    if (request.getPrefetch() == PrefetchBit_Yes) {
365        return; // Ignore the prefetch
366    }
367#endif
368
369    // update the data
370    if (ruby_request.data != NULL) {
371        if ((type == RubyRequestType_LD) ||
372            (type == RubyRequestType_IFETCH) ||
373            (type == RubyRequestType_RMW_Read) ||
374            (type == RubyRequestType_Locked_Read)) {
375
376            memcpy(ruby_request.data,
377                   data.getData(request_address.getOffset(), ruby_request.len),
378                   ruby_request.len);
379        } else {
380            data.setData(ruby_request.data, request_address.getOffset(),
381                         ruby_request.len);
382        }
383    } else {
384        DPRINTF(MemoryAccess,
385                "WARNING.  Data not transfered from Ruby to M5 for type %s\n",
386                RubyRequestType_to_string(type));
387    }
388
389    // If using the RubyTester, update the RubyTester sender state's
390    // subBlock with the recieved data.  The tester will later access
391    // this state.
392    // Note: RubyPort will access it's sender state before the
393    // RubyTester.
394    if (m_usingRubyTester) {
395        RubyPort::SenderState *requestSenderState =
396            safe_cast<RubyPort::SenderState*>(ruby_request.pkt->senderState);
397        RubyTester::SenderState* testerSenderState =
398            safe_cast<RubyTester::SenderState*>(requestSenderState->saved);
399        testerSenderState->subBlock->mergeFrom(data);
400    }
401
402    ruby_hit_callback(ruby_request.pkt);
403    delete srequest;
404}
405
406// Returns true if the sequencer already has a load or store outstanding
407RequestStatus
408Sequencer::getRequestStatus(const RubyRequest& request)
409{
410    bool is_outstanding_store =
411        m_writeRequestTable.exist(line_address(Address(request.paddr)));
412    bool is_outstanding_load =
413        m_readRequestTable.exist(line_address(Address(request.paddr)));
414    if (is_outstanding_store) {
415        if ((request.type == RubyRequestType_LD) ||
416            (request.type == RubyRequestType_IFETCH) ||
417            (request.type == RubyRequestType_RMW_Read)) {
418            m_store_waiting_on_load_cycles++;
419        } else {
420            m_store_waiting_on_store_cycles++;
421        }
422        return RequestStatus_Aliased;
423    } else if (is_outstanding_load) {
424        if ((request.type == RubyRequestType_ST) ||
425            (request.type == RubyRequestType_RMW_Write)) {
426            m_load_waiting_on_store_cycles++;
427        } else {
428            m_load_waiting_on_load_cycles++;
429        }
430        return RequestStatus_Aliased;
431    }
432
433    if (m_outstanding_count >= m_max_outstanding_requests) {
434        return RequestStatus_BufferFull;
435    }
436
437    return RequestStatus_Ready;
438}
439
440bool
441Sequencer::empty() const
442{
443    return m_writeRequestTable.size() == 0 && m_readRequestTable.size() == 0;
444}
445
446RequestStatus
447Sequencer::makeRequest(const RubyRequest &request)
448{
449    assert(Address(request.paddr).getOffset() + request.len <=
450           RubySystem::getBlockSizeBytes());
451    RequestStatus status = getRequestStatus(request);
452    if (status != RequestStatus_Ready)
453        return status;
454
455    SequencerRequest *srequest =
456        new SequencerRequest(request, g_eventQueue_ptr->getTime());
457    bool found = insertRequest(srequest);
458    if (found) {
459        panic("Sequencer::makeRequest should never be called if the "
460              "request is already outstanding\n");
461        return RequestStatus_NULL;
462    }
463
464    if (request.type == RubyRequestType_Locked_Write) {
465        // NOTE: it is OK to check the locked flag here as the
466        // mandatory queue will be checked first ensuring that nothing
467        // comes between checking the flag and servicing the store.
468
469        Address line_addr = line_address(Address(request.paddr));
470        if (!m_dataCache_ptr->isLocked(line_addr, m_version)) {
471            removeRequest(srequest);
472            if (Debug::getProtocolTrace()) {
473                g_system_ptr->getProfiler()->
474                    profileTransition("Seq", m_version,
475                                      Address(request.paddr),
476                                      "", "SC Fail", "",
477                                      RubyRequestType_to_string(request.type));
478            }
479            return RequestStatus_LlscFailed;
480        } else {
481            m_dataCache_ptr->clearLocked(line_addr);
482        }
483    }
484    issueRequest(request);
485
486    // TODO: issue hardware prefetches here
487    return RequestStatus_Issued;
488}
489
490void
491Sequencer::issueRequest(const RubyRequest& request)
492{
493    // TODO: get rid of CacheMsg, CacheRequestType, and
494    // AccessModeTYpe, & have SLICC use RubyRequest and subtypes
495    // natively
496    CacheRequestType ctype;
497    switch(request.type) {
498      case RubyRequestType_IFETCH:
499        ctype = CacheRequestType_IFETCH;
500        break;
501      case RubyRequestType_LD:
502        ctype = CacheRequestType_LD;
503        break;
504      case RubyRequestType_ST:
505        ctype = CacheRequestType_ST;
506        break;
507      case RubyRequestType_Locked_Read:
508      case RubyRequestType_Locked_Write:
509        ctype = CacheRequestType_ATOMIC;
510        break;
511      case RubyRequestType_RMW_Read:
512        ctype = CacheRequestType_ATOMIC;
513        break;
514      case RubyRequestType_RMW_Write:
515        ctype = CacheRequestType_ATOMIC;
516        break;
517      default:
518        assert(0);
519    }
520
521    AccessModeType amtype;
522    switch(request.access_mode){
523      case RubyAccessMode_User:
524        amtype = AccessModeType_UserMode;
525        break;
526      case RubyAccessMode_Supervisor:
527        amtype = AccessModeType_SupervisorMode;
528        break;
529      case RubyAccessMode_Device:
530        amtype = AccessModeType_UserMode;
531        break;
532      default:
533        assert(0);
534    }
535
536    Address line_addr(request.paddr);
537    line_addr.makeLineAddress();
538    CacheMsg msg(line_addr, Address(request.paddr), ctype,
539                 Address(request.pc), amtype, request.len, PrefetchBit_No,
540                 request.proc_id);
541
542    if (Debug::getProtocolTrace()) {
543        g_system_ptr->getProfiler()->
544            profileTransition("Seq", m_version, Address(request.paddr),
545                              "", "Begin", "",
546                              RubyRequestType_to_string(request.type));
547    }
548
549    if (g_system_ptr->getTracer()->traceEnabled()) {
550        g_system_ptr->getTracer()->
551            traceRequest(this, line_addr, Address(request.pc),
552                         request.type, g_eventQueue_ptr->getTime());
553    }
554
555    Time latency = 0;  // initialzed to an null value
556
557    if (request.type == RubyRequestType_IFETCH)
558        latency = m_instCache_ptr->getLatency();
559    else
560        latency = m_dataCache_ptr->getLatency();
561
562    // Send the message to the cache controller
563    assert(latency > 0);
564
565    assert(m_mandatory_q_ptr != NULL);
566    m_mandatory_q_ptr->enqueue(msg, latency);
567}
568
569#if 0
570bool
571Sequencer::tryCacheAccess(const Address& addr, CacheRequestType type,
572                          AccessModeType access_mode,
573                          int size, DataBlock*& data_ptr)
574{
575    CacheMemory *cache =
576        (type == CacheRequestType_IFETCH) ? m_instCache_ptr : m_dataCache_ptr;
577
578    return cache->tryCacheAccess(line_address(addr), type, data_ptr);
579}
580#endif
581
582void
583Sequencer::print(ostream& out) const
584{
585    out << "[Sequencer: " << m_version
586        << ", outstanding requests: " << m_outstanding_count
587        << ", read request table: " << m_readRequestTable
588        << ", write request table: " << m_writeRequestTable
589        << "]";
590}
591
592// this can be called from setState whenever coherence permissions are
593// upgraded when invoked, coherence violations will be checked for the
594// given block
595void
596Sequencer::checkCoherence(const Address& addr)
597{
598#ifdef CHECK_COHERENCE
599    g_system_ptr->checkGlobalCoherenceInvariant(addr);
600#endif
601}
602