Sequencer.cc revision 6763:5a879a3513dc 
1
2/*
3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#include "mem/ruby/common/Global.hh"
31#include "mem/ruby/system/Sequencer.hh"
32#include "mem/ruby/system/System.hh"
33#include "mem/protocol/Protocol.hh"
34#include "mem/ruby/profiler/Profiler.hh"
35#include "mem/ruby/system/CacheMemory.hh"
36#include "mem/protocol/CacheMsg.hh"
37#include "mem/ruby/recorder/Tracer.hh"
38#include "mem/ruby/common/SubBlock.hh"
39#include "mem/protocol/Protocol.hh"
40#include "mem/gems_common/Map.hh"
41#include "mem/ruby/buffers/MessageBuffer.hh"
42#include "mem/ruby/slicc_interface/AbstractController.hh"
43
44//Sequencer::Sequencer(int core_id, MessageBuffer* mandatory_q)
45
46#define LLSC_FAIL -2
47ostream& operator<<(std::ostream& out, const SequencerRequest& obj) {
48  out << obj.ruby_request << flush;
49  return out;
50}
51
52Sequencer::Sequencer(const string & name)
53  :RubyPort(name)
54{
55}
56
57void Sequencer::init(const vector<string> & argv)
58{
59  m_deadlock_check_scheduled = false;
60  m_outstanding_count = 0;
61
62  m_max_outstanding_requests = 0;
63  m_deadlock_threshold = 0;
64  m_version = -1;
65  m_instCache_ptr = NULL;
66  m_dataCache_ptr = NULL;
67  m_controller = NULL;
68  m_servicing_atomic = -1;
69  m_atomics_counter = 0;
70  for (size_t i=0; i<argv.size(); i+=2) {
71    if ( argv[i] == "controller") {
72      m_controller = RubySystem::getController(argv[i+1]); // args[i] = "L1Cache"
73      m_mandatory_q_ptr = m_controller->getMandatoryQueue();
74    } else if ( argv[i] == "icache")
75      m_instCache_ptr = RubySystem::getCache(argv[i+1]);
76    else if ( argv[i] == "dcache")
77      m_dataCache_ptr = RubySystem::getCache(argv[i+1]);
78    else if ( argv[i] == "version")
79      m_version = atoi(argv[i+1].c_str());
80    else if ( argv[i] == "max_outstanding_requests")
81      m_max_outstanding_requests = atoi(argv[i+1].c_str());
82    else if ( argv[i] == "deadlock_threshold")
83      m_deadlock_threshold = atoi(argv[i+1].c_str());
84    else {
85      cerr << "WARNING: Sequencer: Unkown configuration parameter: " << argv[i] << endl;
86      assert(false);
87    }
88  }
89  assert(m_max_outstanding_requests > 0);
90  assert(m_deadlock_threshold > 0);
91  assert(m_version > -1);
92  assert(m_instCache_ptr != NULL);
93  assert(m_dataCache_ptr != NULL);
94  assert(m_controller != NULL);
95}
96
97Sequencer::~Sequencer() {
98
99}
100
101void Sequencer::wakeup() {
102  // Check for deadlock of any of the requests
103  Time current_time = g_eventQueue_ptr->getTime();
104
105  // Check across all outstanding requests
106  int total_outstanding = 0;
107
108  Vector<Address> keys = m_readRequestTable.keys();
109  for (int i=0; i<keys.size(); i++) {
110    SequencerRequest* request = m_readRequestTable.lookup(keys[i]);
111    if (current_time - request->issue_time >= m_deadlock_threshold) {
112      WARN_MSG("Possible Deadlock detected");
113      WARN_EXPR(request->ruby_request);
114      WARN_EXPR(m_version);
115      WARN_EXPR(keys.size());
116      WARN_EXPR(current_time);
117      WARN_EXPR(request->issue_time);
118      WARN_EXPR(current_time - request->issue_time);
119      ERROR_MSG("Aborting");
120    }
121  }
122
123  keys = m_writeRequestTable.keys();
124  for (int i=0; i<keys.size(); i++) {
125    SequencerRequest* request = m_writeRequestTable.lookup(keys[i]);
126    if (current_time - request->issue_time >= m_deadlock_threshold) {
127      WARN_MSG("Possible Deadlock detected");
128      WARN_EXPR(request->ruby_request);
129      WARN_EXPR(m_version);
130      WARN_EXPR(current_time);
131      WARN_EXPR(request->issue_time);
132      WARN_EXPR(current_time - request->issue_time);
133      WARN_EXPR(keys.size());
134      ERROR_MSG("Aborting");
135    }
136  }
137  total_outstanding += m_writeRequestTable.size() + m_readRequestTable.size();
138
139  assert(m_outstanding_count == total_outstanding);
140
141  if (m_outstanding_count > 0) { // If there are still outstanding requests, keep checking
142    g_eventQueue_ptr->scheduleEvent(this, m_deadlock_threshold);
143  } else {
144    m_deadlock_check_scheduled = false;
145  }
146}
147
148void Sequencer::printProgress(ostream& out) const{
149  /*
150  int total_demand = 0;
151  out << "Sequencer Stats Version " << m_version << endl;
152  out << "Current time = " << g_eventQueue_ptr->getTime() << endl;
153  out << "---------------" << endl;
154  out << "outstanding requests" << endl;
155
156  Vector<Address> rkeys = m_readRequestTable.keys();
157  int read_size = rkeys.size();
158  out << "proc " << m_version << " Read Requests = " << read_size << endl;
159  // print the request table
160  for(int i=0; i < read_size; ++i){
161    SequencerRequest * request = m_readRequestTable.lookup(rkeys[i]);
162    out << "\tRequest[ " << i << " ] = " << request->type << " Address " << rkeys[i]  << " Posted " << request->issue_time << " PF " << PrefetchBit_No << endl;
163    total_demand++;
164  }
165
166  Vector<Address> wkeys = m_writeRequestTable.keys();
167  int write_size = wkeys.size();
168  out << "proc " << m_version << " Write Requests = " << write_size << endl;
169  // print the request table
170  for(int i=0; i < write_size; ++i){
171      CacheMsg & request = m_writeRequestTable.lookup(wkeys[i]);
172      out << "\tRequest[ " << i << " ] = " << request.getType() << " Address " << wkeys[i]  << " Posted " << request.getTime() << " PF " << request.getPrefetch() << endl;
173      if( request.getPrefetch() == PrefetchBit_No ){
174        total_demand++;
175      }
176  }
177
178  out << endl;
179
180  out << "Total Number Outstanding: " << m_outstanding_count << endl;
181  out << "Total Number Demand     : " << total_demand << endl;
182  out << "Total Number Prefetches : " << m_outstanding_count - total_demand << endl;
183  out << endl;
184  out << endl;
185  */
186}
187
188void Sequencer::printConfig(ostream& out) const {
189  out << "Seqeuncer config: " << m_name << endl;
190  out << "  controller: " << m_controller->getName() << endl;
191  out << "  version: " << m_version << endl;
192  out << "  max_outstanding_requests: " << m_max_outstanding_requests << endl;
193  out << "  deadlock_threshold: " << m_deadlock_threshold << endl;
194}
195
196// Insert the request on the correct request table.  Return true if
197// the entry was already present.
198bool Sequencer::insertRequest(SequencerRequest* request) {
199  int total_outstanding = m_writeRequestTable.size() + m_readRequestTable.size();
200
201  assert(m_outstanding_count == total_outstanding);
202
203  // See if we should schedule a deadlock check
204  if (m_deadlock_check_scheduled == false) {
205    g_eventQueue_ptr->scheduleEvent(this, m_deadlock_threshold);
206    m_deadlock_check_scheduled = true;
207  }
208
209  Address line_addr(request->ruby_request.paddr);
210  line_addr.makeLineAddress();
211  if ((request->ruby_request.type == RubyRequestType_ST) ||
212      (request->ruby_request.type == RubyRequestType_RMW_Read) ||
213      (request->ruby_request.type == RubyRequestType_RMW_Write) ||
214      (request->ruby_request.type == RubyRequestType_Locked_Read) ||
215      (request->ruby_request.type == RubyRequestType_Locked_Write)) {
216    if (m_writeRequestTable.exist(line_addr)) {
217      m_writeRequestTable.lookup(line_addr) = request;
218      //      return true;
219      assert(0); // drh5: isn't this an error?  do you lose the initial request?
220    }
221    m_writeRequestTable.allocate(line_addr);
222    m_writeRequestTable.lookup(line_addr) = request;
223    m_outstanding_count++;
224  } else {
225    if (m_readRequestTable.exist(line_addr)) {
226      m_readRequestTable.lookup(line_addr) = request;
227      //      return true;
228      assert(0); // drh5: isn't this an error?  do you lose the initial request?
229    }
230    m_readRequestTable.allocate(line_addr);
231    m_readRequestTable.lookup(line_addr) = request;
232    m_outstanding_count++;
233  }
234
235  g_system_ptr->getProfiler()->sequencerRequests(m_outstanding_count);
236
237  total_outstanding = m_writeRequestTable.size() + m_readRequestTable.size();
238  assert(m_outstanding_count == total_outstanding);
239
240  return false;
241}
242
243void Sequencer::removeRequest(SequencerRequest* srequest) {
244
245  assert(m_outstanding_count == m_writeRequestTable.size() + m_readRequestTable.size());
246
247  const RubyRequest & ruby_request = srequest->ruby_request;
248  Address line_addr(ruby_request.paddr);
249  line_addr.makeLineAddress();
250  if ((ruby_request.type == RubyRequestType_ST) ||
251      (ruby_request.type == RubyRequestType_RMW_Read) ||
252      (ruby_request.type == RubyRequestType_RMW_Write) ||
253      (ruby_request.type == RubyRequestType_Locked_Read) ||
254      (ruby_request.type == RubyRequestType_Locked_Write)) {
255    m_writeRequestTable.deallocate(line_addr);
256  } else {
257    m_readRequestTable.deallocate(line_addr);
258  }
259  m_outstanding_count--;
260
261  assert(m_outstanding_count == m_writeRequestTable.size() + m_readRequestTable.size());
262}
263
264void Sequencer::writeCallback(const Address& address, DataBlock& data) {
265
266  assert(address == line_address(address));
267  assert(m_writeRequestTable.exist(line_address(address)));
268
269  SequencerRequest* request = m_writeRequestTable.lookup(address);
270  removeRequest(request);
271
272  assert((request->ruby_request.type == RubyRequestType_ST) ||
273         (request->ruby_request.type == RubyRequestType_RMW_Read) ||
274         (request->ruby_request.type == RubyRequestType_RMW_Write) ||
275         (request->ruby_request.type == RubyRequestType_Locked_Read) ||
276         (request->ruby_request.type == RubyRequestType_Locked_Write));
277  // POLINA: the assumption is that atomics are only on data cache and not instruction cache
278  if (request->ruby_request.type == RubyRequestType_Locked_Read) {
279    m_dataCache_ptr->setLocked(address, m_version);
280  }
281  else if (request->ruby_request.type == RubyRequestType_RMW_Read) {
282    m_controller->set_atomic(address);
283  }
284  else if (request->ruby_request.type == RubyRequestType_RMW_Write) {
285    m_controller->clear_atomic();
286  }
287
288  hitCallback(request, data);
289}
290
291void Sequencer::readCallback(const Address& address, DataBlock& data) {
292
293  assert(address == line_address(address));
294  assert(m_readRequestTable.exist(line_address(address)));
295
296  SequencerRequest* request = m_readRequestTable.lookup(address);
297  removeRequest(request);
298
299  assert((request->ruby_request.type == RubyRequestType_LD) ||
300	 (request->ruby_request.type == RubyRequestType_RMW_Read) ||
301         (request->ruby_request.type == RubyRequestType_IFETCH));
302
303  hitCallback(request, data);
304}
305
306void Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data) {
307  const RubyRequest & ruby_request = srequest->ruby_request;
308  Address request_address(ruby_request.paddr);
309  Address request_line_address(ruby_request.paddr);
310  request_line_address.makeLineAddress();
311  RubyRequestType type = ruby_request.type;
312  Time issued_time = srequest->issue_time;
313
314  // Set this cache entry to the most recently used
315  if (type == RubyRequestType_IFETCH) {
316    if (m_instCache_ptr->isTagPresent(request_line_address) )
317      m_instCache_ptr->setMRU(request_line_address);
318  } else {
319    if (m_dataCache_ptr->isTagPresent(request_line_address) )
320      m_dataCache_ptr->setMRU(request_line_address);
321  }
322
323  assert(g_eventQueue_ptr->getTime() >= issued_time);
324  Time miss_latency = g_eventQueue_ptr->getTime() - issued_time;
325
326  // Profile the miss latency for all non-zero demand misses
327  if (miss_latency != 0) {
328    g_system_ptr->getProfiler()->missLatency(miss_latency, type);
329
330    if (Debug::getProtocolTrace()) {
331      g_system_ptr->getProfiler()->profileTransition("Seq", m_version, Address(ruby_request.paddr),
332                                                     "", "Done", "", int_to_string(miss_latency)+" cycles");
333    }
334  }
335  /*
336  if (request.getPrefetch() == PrefetchBit_Yes) {
337    return; // Ignore the prefetch
338  }
339  */
340
341  // update the data
342  if (ruby_request.data != NULL) {
343    if ((type == RubyRequestType_LD) ||
344        (type == RubyRequestType_IFETCH) ||
345        (type == RubyRequestType_RMW_Read)) {
346      memcpy(ruby_request.data, data.getData(request_address.getOffset(), ruby_request.len), ruby_request.len);
347    } else {
348      data.setData(ruby_request.data, request_address.getOffset(), ruby_request.len);
349    }
350  }
351
352  m_hit_callback(srequest->id);
353  delete srequest;
354}
355
356// Returns true if the sequencer already has a load or store outstanding
357bool Sequencer::isReady(const RubyRequest& request) {
358  // POLINA: check if we are currently flushing the write buffer, if so Ruby is returned as not ready
359  // to simulate stalling of the front-end
360  // Do we stall all the sequencers? If it is atomic instruction - yes!
361  if (m_outstanding_count >= m_max_outstanding_requests) {
362    return false;
363  }
364
365  if( m_writeRequestTable.exist(line_address(Address(request.paddr))) ||
366      m_readRequestTable.exist(line_address(Address(request.paddr))) ){
367    //cout << "OUTSTANDING REQUEST EXISTS " << p << " VER " << m_version << endl;
368    //printProgress(cout);
369    return false;
370  }
371
372  if (m_servicing_atomic != -1 && m_servicing_atomic != (int)request.proc_id) {
373    assert(m_atomics_counter > 0);
374    return false;
375  }
376  else {
377    if (request.type == RubyRequestType_RMW_Read) {
378      if (m_servicing_atomic == -1) {
379        assert(m_atomics_counter == 0);
380        m_servicing_atomic = (int)request.proc_id;
381      }
382      else {
383        assert(m_servicing_atomic == (int)request.proc_id);
384      }
385      m_atomics_counter++;
386    }
387    else if (request.type == RubyRequestType_RMW_Write) {
388      assert(m_servicing_atomic == (int)request.proc_id);
389      assert(m_atomics_counter > 0);
390      m_atomics_counter--;
391      if (m_atomics_counter == 0) {
392        m_servicing_atomic = -1;
393      }
394    }
395  }
396
397  return true;
398}
399
400bool Sequencer::empty() const {
401  return (m_writeRequestTable.size() == 0) && (m_readRequestTable.size() == 0);
402}
403
404
405int64_t Sequencer::makeRequest(const RubyRequest & request)
406{
407  assert(Address(request.paddr).getOffset() + request.len <= RubySystem::getBlockSizeBytes());
408  if (isReady(request)) {
409    int64_t id = makeUniqueRequestID();
410    SequencerRequest *srequest = new SequencerRequest(request, id, g_eventQueue_ptr->getTime());
411    bool found = insertRequest(srequest);
412    if (!found)
413      if (request.type == RubyRequestType_Locked_Write) {
414        // NOTE: it is OK to check the locked flag here as the mandatory queue will be checked first
415        // ensuring that nothing comes between checking the flag and servicing the store
416        if (!m_dataCache_ptr->isLocked(line_address(Address(request.paddr)), m_version)) {
417          return LLSC_FAIL;
418        }
419        else {
420          m_dataCache_ptr->clearLocked(line_address(Address(request.paddr)));
421        }
422      }
423      if (request.type == RubyRequestType_RMW_Write) {
424        m_controller->started_writes();
425      }
426      issueRequest(request);
427
428    // TODO: issue hardware prefetches here
429    return id;
430  }
431  else {
432    return -1;
433  }
434}
435
436void Sequencer::issueRequest(const RubyRequest& request) {
437
438  // TODO: get rid of CacheMsg, CacheRequestType, and AccessModeTYpe, & have SLICC use RubyRequest and subtypes natively
439  CacheRequestType ctype;
440  switch(request.type) {
441  case RubyRequestType_IFETCH:
442    ctype = CacheRequestType_IFETCH;
443    break;
444  case RubyRequestType_LD:
445    ctype = CacheRequestType_LD;
446    break;
447  case RubyRequestType_ST:
448    ctype = CacheRequestType_ST;
449    break;
450  case RubyRequestType_Locked_Read:
451    ctype = CacheRequestType_ST;
452    break;
453  case RubyRequestType_Locked_Write:
454    ctype = CacheRequestType_ST;
455    break;
456  case RubyRequestType_RMW_Read:
457    ctype = CacheRequestType_ATOMIC;
458    break;
459  case RubyRequestType_RMW_Write:
460    ctype = CacheRequestType_ATOMIC;
461    break;
462  default:
463    assert(0);
464  }
465  AccessModeType amtype;
466  switch(request.access_mode){
467  case RubyAccessMode_User:
468    amtype = AccessModeType_UserMode;
469    break;
470  case RubyAccessMode_Supervisor:
471    amtype = AccessModeType_SupervisorMode;
472    break;
473  case RubyAccessMode_Device:
474    amtype = AccessModeType_UserMode;
475    break;
476  default:
477    assert(0);
478  }
479  Address line_addr(request.paddr);
480  line_addr.makeLineAddress();
481  CacheMsg msg(line_addr, Address(request.paddr), ctype, Address(request.pc), amtype, request.len, PrefetchBit_No, request.proc_id);
482
483  if (Debug::getProtocolTrace()) {
484    g_system_ptr->getProfiler()->profileTransition("Seq", m_version, Address(request.paddr),
485                                                   "", "Begin", "", RubyRequestType_to_string(request.type));
486  }
487
488  if (g_system_ptr->getTracer()->traceEnabled()) {
489    g_system_ptr->getTracer()->traceRequest(m_name, line_addr, Address(request.pc),
490                                            request.type, g_eventQueue_ptr->getTime());
491  }
492
493  Time latency = 0;  // initialzed to an null value
494
495  if (request.type == RubyRequestType_IFETCH)
496    latency = m_instCache_ptr->getLatency();
497  else
498    latency = m_dataCache_ptr->getLatency();
499
500  // Send the message to the cache controller
501  assert(latency > 0);
502
503
504  m_mandatory_q_ptr->enqueue(msg, latency);
505}
506/*
507bool Sequencer::tryCacheAccess(const Address& addr, CacheRequestType type,
508                               AccessModeType access_mode,
509                               int size, DataBlock*& data_ptr) {
510  if (type == CacheRequestType_IFETCH) {
511    return m_instCache_ptr->tryCacheAccess(line_address(addr), type, data_ptr);
512  } else {
513    return m_dataCache_ptr->tryCacheAccess(line_address(addr), type, data_ptr);
514  }
515}
516*/
517
518void Sequencer::print(ostream& out) const {
519  out << "[Sequencer: " << m_version
520      << ", outstanding requests: " << m_outstanding_count;
521
522  out << ", read request table: " << m_readRequestTable
523      << ", write request table: " << m_writeRequestTable;
524  out << "]";
525}
526
527// this can be called from setState whenever coherence permissions are upgraded
528// when invoked, coherence violations will be checked for the given block
529void Sequencer::checkCoherence(const Address& addr) {
530#ifdef CHECK_COHERENCE
531  g_system_ptr->checkGlobalCoherenceInvariant(addr);
532#endif
533}
534
535