Sequencer.cc revision 6381:fb39bf847dbe
1 2/* 3 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; 10 * redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution; 13 * neither the name of the copyright holders nor the names of its 14 * contributors may be used to endorse or promote products derived from 15 * this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30#include "mem/ruby/common/Global.hh" 31#include "mem/ruby/system/Sequencer.hh" 32#include "mem/ruby/system/System.hh" 33#include "mem/protocol/Protocol.hh" 34#include "mem/ruby/profiler/Profiler.hh" 35#include "mem/ruby/system/CacheMemory.hh" 36#include "mem/protocol/CacheMsg.hh" 37#include "mem/ruby/recorder/Tracer.hh" 38#include "mem/ruby/common/SubBlock.hh" 39#include "mem/protocol/Protocol.hh" 40#include "mem/gems_common/Map.hh" 41#include "mem/ruby/buffers/MessageBuffer.hh" 42#include "mem/ruby/slicc_interface/AbstractController.hh" 43 44//Sequencer::Sequencer(int core_id, MessageBuffer* mandatory_q) 45 46#define LLSC_FAIL -2 47 48Sequencer::Sequencer(const string & name) 49 :RubyPort(name) 50{ 51} 52 53void Sequencer::init(const vector<string> & argv) 54{ 55 m_deadlock_check_scheduled = false; 56 m_outstanding_count = 0; 57 58 m_max_outstanding_requests = 0; 59 m_deadlock_threshold = 0; 60 m_version = -1; 61 m_instCache_ptr = NULL; 62 m_dataCache_ptr = NULL; 63 m_controller = NULL; 64 for (size_t i=0; i<argv.size(); i+=2) { 65 if ( argv[i] == "controller") { 66 m_controller = RubySystem::getController(argv[i+1]); // args[i] = "L1Cache" 67 m_mandatory_q_ptr = m_controller->getMandatoryQueue(); 68 } else if ( argv[i] == "icache") 69 m_instCache_ptr = RubySystem::getCache(argv[i+1]); 70 else if ( argv[i] == "dcache") 71 m_dataCache_ptr = RubySystem::getCache(argv[i+1]); 72 else if ( argv[i] == "version") 73 m_version = atoi(argv[i+1].c_str()); 74 else if ( argv[i] == "max_outstanding_requests") 75 m_max_outstanding_requests = atoi(argv[i+1].c_str()); 76 else if ( argv[i] == "deadlock_threshold") 77 m_deadlock_threshold = atoi(argv[i+1].c_str()); 78 else { 79 cerr << "WARNING: Sequencer: Unkown configuration parameter: " << argv[i] << endl; 80 assert(false); 81 } 82 } 83 assert(m_max_outstanding_requests > 0); 84 assert(m_deadlock_threshold > 0); 85 assert(m_version > -1); 86 assert(m_instCache_ptr != NULL); 87 assert(m_dataCache_ptr != NULL); 88 assert(m_controller != NULL); 89} 90 91Sequencer::~Sequencer() { 92 93} 94 95void Sequencer::wakeup() { 96 // Check for deadlock of any of the requests 97 Time current_time = g_eventQueue_ptr->getTime(); 98 99 // Check across all outstanding requests 100 int total_outstanding = 0; 101 102 Vector<Address> keys = m_readRequestTable.keys(); 103 for (int i=0; i<keys.size(); i++) { 104 SequencerRequest* request = m_readRequestTable.lookup(keys[i]); 105 if (current_time - request->issue_time >= m_deadlock_threshold) { 106 WARN_MSG("Possible Deadlock detected"); 107 WARN_EXPR(request); 108 WARN_EXPR(m_version); 109 WARN_EXPR(keys.size()); 110 WARN_EXPR(current_time); 111 WARN_EXPR(request->issue_time); 112 WARN_EXPR(current_time - request->issue_time); 113 ERROR_MSG("Aborting"); 114 } 115 } 116 117 keys = m_writeRequestTable.keys(); 118 for (int i=0; i<keys.size(); i++) { 119 SequencerRequest* request = m_writeRequestTable.lookup(keys[i]); 120 if (current_time - request->issue_time >= m_deadlock_threshold) { 121 WARN_MSG("Possible Deadlock detected"); 122 WARN_EXPR(request); 123 WARN_EXPR(m_version); 124 WARN_EXPR(current_time); 125 WARN_EXPR(request->issue_time); 126 WARN_EXPR(current_time - request->issue_time); 127 WARN_EXPR(keys.size()); 128 ERROR_MSG("Aborting"); 129 } 130 } 131 total_outstanding += m_writeRequestTable.size() + m_readRequestTable.size(); 132 133 assert(m_outstanding_count == total_outstanding); 134 135 if (m_outstanding_count > 0) { // If there are still outstanding requests, keep checking 136 g_eventQueue_ptr->scheduleEvent(this, m_deadlock_threshold); 137 } else { 138 m_deadlock_check_scheduled = false; 139 } 140} 141 142void Sequencer::printProgress(ostream& out) const{ 143 /* 144 int total_demand = 0; 145 out << "Sequencer Stats Version " << m_version << endl; 146 out << "Current time = " << g_eventQueue_ptr->getTime() << endl; 147 out << "---------------" << endl; 148 out << "outstanding requests" << endl; 149 150 Vector<Address> rkeys = m_readRequestTable.keys(); 151 int read_size = rkeys.size(); 152 out << "proc " << m_version << " Read Requests = " << read_size << endl; 153 // print the request table 154 for(int i=0; i < read_size; ++i){ 155 SequencerRequest * request = m_readRequestTable.lookup(rkeys[i]); 156 out << "\tRequest[ " << i << " ] = " << request->type << " Address " << rkeys[i] << " Posted " << request->issue_time << " PF " << PrefetchBit_No << endl; 157 total_demand++; 158 } 159 160 Vector<Address> wkeys = m_writeRequestTable.keys(); 161 int write_size = wkeys.size(); 162 out << "proc " << m_version << " Write Requests = " << write_size << endl; 163 // print the request table 164 for(int i=0; i < write_size; ++i){ 165 CacheMsg & request = m_writeRequestTable.lookup(wkeys[i]); 166 out << "\tRequest[ " << i << " ] = " << request.getType() << " Address " << wkeys[i] << " Posted " << request.getTime() << " PF " << request.getPrefetch() << endl; 167 if( request.getPrefetch() == PrefetchBit_No ){ 168 total_demand++; 169 } 170 } 171 172 out << endl; 173 174 out << "Total Number Outstanding: " << m_outstanding_count << endl; 175 out << "Total Number Demand : " << total_demand << endl; 176 out << "Total Number Prefetches : " << m_outstanding_count - total_demand << endl; 177 out << endl; 178 out << endl; 179 */ 180} 181 182void Sequencer::printConfig(ostream& out) const { 183 out << "Seqeuncer config: " << m_name << endl; 184 out << " controller: " << m_controller->getName() << endl; 185 out << " version: " << m_version << endl; 186 out << " max_outstanding_requests: " << m_max_outstanding_requests << endl; 187 out << " deadlock_threshold: " << m_deadlock_threshold << endl; 188} 189 190// Insert the request on the correct request table. Return true if 191// the entry was already present. 192bool Sequencer::insertRequest(SequencerRequest* request) { 193 int total_outstanding = m_writeRequestTable.size() + m_readRequestTable.size(); 194 195 assert(m_outstanding_count == total_outstanding); 196 197 // See if we should schedule a deadlock check 198 if (m_deadlock_check_scheduled == false) { 199 g_eventQueue_ptr->scheduleEvent(this, m_deadlock_threshold); 200 m_deadlock_check_scheduled = true; 201 } 202 203 Address line_addr(request->ruby_request.paddr); 204 line_addr.makeLineAddress(); 205 if ((request->ruby_request.type == RubyRequestType_ST) || 206 (request->ruby_request.type == RubyRequestType_RMW_Read) || 207 (request->ruby_request.type == RubyRequestType_RMW_Write) || 208 (request->ruby_request.type == RubyRequestType_Locked_Read) || 209 (request->ruby_request.type == RubyRequestType_Locked_Write)) { 210 if (m_writeRequestTable.exist(line_addr)) { 211 m_writeRequestTable.lookup(line_addr) = request; 212 // return true; 213 assert(0); // drh5: isn't this an error? do you lose the initial request? 214 } 215 m_writeRequestTable.allocate(line_addr); 216 m_writeRequestTable.lookup(line_addr) = request; 217 m_outstanding_count++; 218 } else { 219 if (m_readRequestTable.exist(line_addr)) { 220 m_readRequestTable.lookup(line_addr) = request; 221 // return true; 222 assert(0); // drh5: isn't this an error? do you lose the initial request? 223 } 224 m_readRequestTable.allocate(line_addr); 225 m_readRequestTable.lookup(line_addr) = request; 226 m_outstanding_count++; 227 } 228 229 g_system_ptr->getProfiler()->sequencerRequests(m_outstanding_count); 230 231 total_outstanding = m_writeRequestTable.size() + m_readRequestTable.size(); 232 assert(m_outstanding_count == total_outstanding); 233 234 return false; 235} 236 237void Sequencer::removeRequest(SequencerRequest* srequest) { 238 239 assert(m_outstanding_count == m_writeRequestTable.size() + m_readRequestTable.size()); 240 241 const RubyRequest & ruby_request = srequest->ruby_request; 242 Address line_addr(ruby_request.paddr); 243 line_addr.makeLineAddress(); 244 if ((ruby_request.type == RubyRequestType_ST) || 245 (ruby_request.type == RubyRequestType_RMW_Read) || 246 (ruby_request.type == RubyRequestType_RMW_Write) || 247 (ruby_request.type == RubyRequestType_Locked_Read) || 248 (ruby_request.type == RubyRequestType_Locked_Write)) { 249 m_writeRequestTable.deallocate(line_addr); 250 } else { 251 m_readRequestTable.deallocate(line_addr); 252 } 253 m_outstanding_count--; 254 255 assert(m_outstanding_count == m_writeRequestTable.size() + m_readRequestTable.size()); 256} 257 258void Sequencer::writeCallback(const Address& address, DataBlock& data) { 259 260 assert(address == line_address(address)); 261 assert(m_writeRequestTable.exist(line_address(address))); 262 263 SequencerRequest* request = m_writeRequestTable.lookup(address); 264 removeRequest(request); 265 266 assert((request->ruby_request.type == RubyRequestType_ST) || 267 (request->ruby_request.type == RubyRequestType_RMW_Read) || 268 (request->ruby_request.type == RubyRequestType_RMW_Write) || 269 (request->ruby_request.type == RubyRequestType_Locked_Read) || 270 (request->ruby_request.type == RubyRequestType_Locked_Write)); 271 // POLINA: the assumption is that atomics are only on data cache and not instruction cache 272 if (request->ruby_request.type == RubyRequestType_Locked_Read) { 273 m_dataCache_ptr->setLocked(address, m_version); 274 } 275 276 hitCallback(request, data); 277} 278 279void Sequencer::readCallback(const Address& address, DataBlock& data) { 280 281 assert(address == line_address(address)); 282 assert(m_readRequestTable.exist(line_address(address))); 283 284 SequencerRequest* request = m_readRequestTable.lookup(address); 285 removeRequest(request); 286 287 assert((request->ruby_request.type == RubyRequestType_LD) || 288 (request->ruby_request.type == RubyRequestType_RMW_Read) || 289 (request->ruby_request.type == RubyRequestType_IFETCH)); 290 291 hitCallback(request, data); 292} 293 294void Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data) { 295 const RubyRequest & ruby_request = srequest->ruby_request; 296 Address request_address(ruby_request.paddr); 297 Address request_line_address(ruby_request.paddr); 298 request_line_address.makeLineAddress(); 299 RubyRequestType type = ruby_request.type; 300 Time issued_time = srequest->issue_time; 301 302 // Set this cache entry to the most recently used 303 if (type == RubyRequestType_IFETCH) { 304 if (m_instCache_ptr->isTagPresent(request_line_address) ) 305 m_instCache_ptr->setMRU(request_line_address); 306 } else { 307 if (m_dataCache_ptr->isTagPresent(request_line_address) ) 308 m_dataCache_ptr->setMRU(request_line_address); 309 } 310 311 assert(g_eventQueue_ptr->getTime() >= issued_time); 312 Time miss_latency = g_eventQueue_ptr->getTime() - issued_time; 313 314 // Profile the miss latency for all non-zero demand misses 315 if (miss_latency != 0) { 316 g_system_ptr->getProfiler()->missLatency(miss_latency, type); 317 318 if (Debug::getProtocolTrace()) { 319 g_system_ptr->getProfiler()->profileTransition("Seq", m_version, Address(ruby_request.paddr), 320 "", "Done", "", int_to_string(miss_latency)+" cycles"); 321 } 322 } 323 /* 324 if (request.getPrefetch() == PrefetchBit_Yes) { 325 return; // Ignore the prefetch 326 } 327 */ 328 329 // update the data 330 if (ruby_request.data != NULL) { 331 if ((type == RubyRequestType_LD) || 332 (type == RubyRequestType_IFETCH) || 333 (type == RubyRequestType_RMW_Read)) { 334 memcpy(ruby_request.data, data.getData(request_address.getOffset(), ruby_request.len), ruby_request.len); 335 } else { 336 data.setData(ruby_request.data, request_address.getOffset(), ruby_request.len); 337 } 338 } 339 340 m_hit_callback(srequest->id); 341 delete srequest; 342} 343 344// Returns true if the sequencer already has a load or store outstanding 345bool Sequencer::isReady(const RubyRequest& request) const { 346 // POLINA: check if we are currently flushing the write buffer, if so Ruby is returned as not ready 347 // to simulate stalling of the front-end 348 // Do we stall all the sequencers? If it is atomic instruction - yes! 349 if (m_outstanding_count >= m_max_outstanding_requests) { 350 return false; 351 } 352 353 if( m_writeRequestTable.exist(line_address(Address(request.paddr))) || 354 m_readRequestTable.exist(line_address(Address(request.paddr))) ){ 355 //cout << "OUTSTANDING REQUEST EXISTS " << p << " VER " << m_version << endl; 356 //printProgress(cout); 357 return false; 358 } 359 360 return true; 361} 362 363bool Sequencer::empty() const { 364 return (m_writeRequestTable.size() == 0) && (m_readRequestTable.size() == 0); 365} 366 367 368int64_t Sequencer::makeRequest(const RubyRequest & request) 369{ 370 assert(Address(request.paddr).getOffset() + request.len <= RubySystem::getBlockSizeBytes()); 371 if (isReady(request)) { 372 int64_t id = makeUniqueRequestID(); 373 SequencerRequest *srequest = new SequencerRequest(request, id, g_eventQueue_ptr->getTime()); 374 bool found = insertRequest(srequest); 375 if (!found) 376 if (request.type == RubyRequestType_Locked_Write) { 377 // NOTE: it is OK to check the locked flag here as the mandatory queue will be checked first 378 // ensuring that nothing comes between checking the flag and servicing the store 379 if (!m_dataCache_ptr->isLocked(line_address(Address(request.paddr)), m_version)) { 380 return LLSC_FAIL; 381 } 382 else { 383 m_dataCache_ptr->clearLocked(line_address(Address(request.paddr))); 384 } 385 } 386 issueRequest(request); 387 388 // TODO: issue hardware prefetches here 389 return id; 390 } 391 else { 392 return -1; 393 } 394} 395 396void Sequencer::issueRequest(const RubyRequest& request) { 397 398 // TODO: get rid of CacheMsg, CacheRequestType, and AccessModeTYpe, & have SLICC use RubyRequest and subtypes natively 399 CacheRequestType ctype; 400 switch(request.type) { 401 case RubyRequestType_IFETCH: 402 ctype = CacheRequestType_IFETCH; 403 break; 404 case RubyRequestType_LD: 405 ctype = CacheRequestType_LD; 406 break; 407 case RubyRequestType_ST: 408 ctype = CacheRequestType_ST; 409 break; 410 case RubyRequestType_Locked_Read: 411 ctype = CacheRequestType_ST; 412 break; 413 case RubyRequestType_Locked_Write: 414 ctype = CacheRequestType_ST; 415 break; 416 case RubyRequestType_RMW_Read: 417 ctype = CacheRequestType_ATOMIC; 418 break; 419 case RubyRequestType_RMW_Write: 420 ctype = CacheRequestType_ATOMIC; 421 break; 422 default: 423 assert(0); 424 } 425 AccessModeType amtype; 426 switch(request.access_mode){ 427 case RubyAccessMode_User: 428 amtype = AccessModeType_UserMode; 429 break; 430 case RubyAccessMode_Supervisor: 431 amtype = AccessModeType_SupervisorMode; 432 break; 433 case RubyAccessMode_Device: 434 amtype = AccessModeType_UserMode; 435 break; 436 default: 437 assert(0); 438 } 439 Address line_addr(request.paddr); 440 line_addr.makeLineAddress(); 441 CacheMsg msg(line_addr, Address(request.paddr), ctype, Address(request.pc), amtype, request.len, PrefetchBit_No); 442 443 if (Debug::getProtocolTrace()) { 444 g_system_ptr->getProfiler()->profileTransition("Seq", m_version, Address(request.paddr), 445 "", "Begin", "", RubyRequestType_to_string(request.type)); 446 } 447 448 if (g_system_ptr->getTracer()->traceEnabled()) { 449 g_system_ptr->getTracer()->traceRequest(m_name, line_addr, Address(request.pc), 450 request.type, g_eventQueue_ptr->getTime()); 451 } 452 453 Time latency = 0; // initialzed to an null value 454 455 if (request.type == RubyRequestType_IFETCH) 456 latency = m_instCache_ptr->getLatency(); 457 else 458 latency = m_dataCache_ptr->getLatency(); 459 460 // Send the message to the cache controller 461 assert(latency > 0); 462 463 464 m_mandatory_q_ptr->enqueue(msg, latency); 465} 466/* 467bool Sequencer::tryCacheAccess(const Address& addr, CacheRequestType type, 468 AccessModeType access_mode, 469 int size, DataBlock*& data_ptr) { 470 if (type == CacheRequestType_IFETCH) { 471 return m_instCache_ptr->tryCacheAccess(line_address(addr), type, data_ptr); 472 } else { 473 return m_dataCache_ptr->tryCacheAccess(line_address(addr), type, data_ptr); 474 } 475} 476*/ 477 478void Sequencer::print(ostream& out) const { 479 out << "[Sequencer: " << m_version 480 << ", outstanding requests: " << m_outstanding_count; 481 482 out << ", read request table: " << m_readRequestTable 483 << ", write request table: " << m_writeRequestTable; 484 out << "]"; 485} 486 487// this can be called from setState whenever coherence permissions are upgraded 488// when invoked, coherence violations will be checked for the given block 489void Sequencer::checkCoherence(const Address& addr) { 490#ifdef CHECK_COHERENCE 491 g_system_ptr->checkGlobalCoherenceInvariant(addr); 492#endif 493} 494 495