Sequencer.cc revision 11049
1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include "arch/x86/ldstflags.hh" 30#include "base/misc.hh" 31#include "base/str.hh" 32#include "cpu/testers/rubytest/RubyTester.hh" 33#include "debug/MemoryAccess.hh" 34#include "debug/ProtocolTrace.hh" 35#include "debug/RubySequencer.hh" 36#include "debug/RubyStats.hh" 37#include "mem/protocol/PrefetchBit.hh" 38#include "mem/protocol/RubyAccessMode.hh" 39#include "mem/ruby/profiler/Profiler.hh" 40#include "mem/ruby/slicc_interface/RubyRequest.hh" 41#include "mem/ruby/system/Sequencer.hh" 42#include "mem/ruby/system/System.hh" 43#include "mem/packet.hh" 44#include "sim/system.hh" 45 46using namespace std; 47 48Sequencer * 49RubySequencerParams::create() 50{ 51 return new Sequencer(this); 52} 53 54Sequencer::Sequencer(const Params *p) 55 : RubyPort(p), m_IncompleteTimes(MachineType_NUM), deadlockCheckEvent(this) 56{ 57 m_outstanding_count = 0; 58 59 m_instCache_ptr = p->icache; 60 m_dataCache_ptr = p->dcache; 61 m_data_cache_hit_latency = p->dcache_hit_latency; 62 m_inst_cache_hit_latency = p->icache_hit_latency; 63 m_max_outstanding_requests = p->max_outstanding_requests; 64 m_deadlock_threshold = p->deadlock_threshold; 65 66 assert(m_max_outstanding_requests > 0); 67 assert(m_deadlock_threshold > 0); 68 assert(m_instCache_ptr != NULL); 69 assert(m_dataCache_ptr != NULL); 70 assert(m_data_cache_hit_latency > 0); 71 assert(m_inst_cache_hit_latency > 0); 72 73 m_usingNetworkTester = p->using_network_tester; 74} 75 76Sequencer::~Sequencer() 77{ 78} 79 80void 81Sequencer::wakeup() 82{ 83 assert(drainState() != DrainState::Draining); 84 85 // Check for deadlock of any of the requests 86 Cycles current_time = curCycle(); 87 88 // Check across all outstanding requests 89 int total_outstanding = 0; 90 91 RequestTable::iterator read = m_readRequestTable.begin(); 92 RequestTable::iterator read_end = m_readRequestTable.end(); 93 for (; read != read_end; ++read) { 94 SequencerRequest* request = read->second; 95 if (current_time - request->issue_time < m_deadlock_threshold) 96 continue; 97 98 panic("Possible Deadlock detected. Aborting!\n" 99 "version: %d request.paddr: 0x%x m_readRequestTable: %d " 100 "current time: %u issue_time: %d difference: %d\n", m_version, 101 request->pkt->getAddr(), m_readRequestTable.size(), 102 current_time * clockPeriod(), request->issue_time * clockPeriod(), 103 (current_time * clockPeriod()) - (request->issue_time * clockPeriod())); 104 } 105 106 RequestTable::iterator write = m_writeRequestTable.begin(); 107 RequestTable::iterator write_end = m_writeRequestTable.end(); 108 for (; write != write_end; ++write) { 109 SequencerRequest* request = write->second; 110 if (current_time - request->issue_time < m_deadlock_threshold) 111 continue; 112 113 panic("Possible Deadlock detected. Aborting!\n" 114 "version: %d request.paddr: 0x%x m_writeRequestTable: %d " 115 "current time: %u issue_time: %d difference: %d\n", m_version, 116 request->pkt->getAddr(), m_writeRequestTable.size(), 117 current_time * clockPeriod(), request->issue_time * clockPeriod(), 118 (current_time * clockPeriod()) - (request->issue_time * clockPeriod())); 119 } 120 121 total_outstanding += m_writeRequestTable.size(); 122 total_outstanding += m_readRequestTable.size(); 123 124 assert(m_outstanding_count == total_outstanding); 125 126 if (m_outstanding_count > 0) { 127 // If there are still outstanding requests, keep checking 128 schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold)); 129 } 130} 131 132void Sequencer::resetStats() 133{ 134 m_latencyHist.reset(); 135 m_hitLatencyHist.reset(); 136 m_missLatencyHist.reset(); 137 for (int i = 0; i < RubyRequestType_NUM; i++) { 138 m_typeLatencyHist[i]->reset(); 139 m_hitTypeLatencyHist[i]->reset(); 140 m_missTypeLatencyHist[i]->reset(); 141 for (int j = 0; j < MachineType_NUM; j++) { 142 m_hitTypeMachLatencyHist[i][j]->reset(); 143 m_missTypeMachLatencyHist[i][j]->reset(); 144 } 145 } 146 147 for (int i = 0; i < MachineType_NUM; i++) { 148 m_missMachLatencyHist[i]->reset(); 149 m_hitMachLatencyHist[i]->reset(); 150 151 m_IssueToInitialDelayHist[i]->reset(); 152 m_InitialToForwardDelayHist[i]->reset(); 153 m_ForwardToFirstResponseDelayHist[i]->reset(); 154 m_FirstResponseToCompletionDelayHist[i]->reset(); 155 156 m_IncompleteTimes[i] = 0; 157 } 158} 159 160void 161Sequencer::printProgress(ostream& out) const 162{ 163#if 0 164 int total_demand = 0; 165 out << "Sequencer Stats Version " << m_version << endl; 166 out << "Current time = " << m_ruby_system->getTime() << endl; 167 out << "---------------" << endl; 168 out << "outstanding requests" << endl; 169 170 out << "proc " << m_Read 171 << " version Requests = " << m_readRequestTable.size() << endl; 172 173 // print the request table 174 RequestTable::iterator read = m_readRequestTable.begin(); 175 RequestTable::iterator read_end = m_readRequestTable.end(); 176 for (; read != read_end; ++read) { 177 SequencerRequest* request = read->second; 178 out << "\tRequest[ " << i << " ] = " << request->type 179 << " Address " << rkeys[i] 180 << " Posted " << request->issue_time 181 << " PF " << PrefetchBit_No << endl; 182 total_demand++; 183 } 184 185 out << "proc " << m_version 186 << " Write Requests = " << m_writeRequestTable.size << endl; 187 188 // print the request table 189 RequestTable::iterator write = m_writeRequestTable.begin(); 190 RequestTable::iterator write_end = m_writeRequestTable.end(); 191 for (; write != write_end; ++write) { 192 SequencerRequest* request = write->second; 193 out << "\tRequest[ " << i << " ] = " << request.getType() 194 << " Address " << wkeys[i] 195 << " Posted " << request.getTime() 196 << " PF " << request.getPrefetch() << endl; 197 if (request.getPrefetch() == PrefetchBit_No) { 198 total_demand++; 199 } 200 } 201 202 out << endl; 203 204 out << "Total Number Outstanding: " << m_outstanding_count << endl 205 << "Total Number Demand : " << total_demand << endl 206 << "Total Number Prefetches : " << m_outstanding_count - total_demand 207 << endl << endl << endl; 208#endif 209} 210 211// Insert the request on the correct request table. Return true if 212// the entry was already present. 213RequestStatus 214Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type) 215{ 216 assert(m_outstanding_count == 217 (m_writeRequestTable.size() + m_readRequestTable.size())); 218 219 // See if we should schedule a deadlock check 220 if (!deadlockCheckEvent.scheduled() && 221 drainState() != DrainState::Draining) { 222 schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold)); 223 } 224 225 Addr line_addr = makeLineAddress(pkt->getAddr()); 226 // Create a default entry, mapping the address to NULL, the cast is 227 // there to make gcc 4.4 happy 228 RequestTable::value_type default_entry(line_addr, 229 (SequencerRequest*) NULL); 230 231 if ((request_type == RubyRequestType_ST) || 232 (request_type == RubyRequestType_RMW_Read) || 233 (request_type == RubyRequestType_RMW_Write) || 234 (request_type == RubyRequestType_Load_Linked) || 235 (request_type == RubyRequestType_Store_Conditional) || 236 (request_type == RubyRequestType_Locked_RMW_Read) || 237 (request_type == RubyRequestType_Locked_RMW_Write) || 238 (request_type == RubyRequestType_FLUSH)) { 239 240 // Check if there is any outstanding read request for the same 241 // cache line. 242 if (m_readRequestTable.count(line_addr) > 0) { 243 m_store_waiting_on_load++; 244 return RequestStatus_Aliased; 245 } 246 247 pair<RequestTable::iterator, bool> r = 248 m_writeRequestTable.insert(default_entry); 249 if (r.second) { 250 RequestTable::iterator i = r.first; 251 i->second = new SequencerRequest(pkt, request_type, curCycle()); 252 m_outstanding_count++; 253 } else { 254 // There is an outstanding write request for the cache line 255 m_store_waiting_on_store++; 256 return RequestStatus_Aliased; 257 } 258 } else { 259 // Check if there is any outstanding write request for the same 260 // cache line. 261 if (m_writeRequestTable.count(line_addr) > 0) { 262 m_load_waiting_on_store++; 263 return RequestStatus_Aliased; 264 } 265 266 pair<RequestTable::iterator, bool> r = 267 m_readRequestTable.insert(default_entry); 268 269 if (r.second) { 270 RequestTable::iterator i = r.first; 271 i->second = new SequencerRequest(pkt, request_type, curCycle()); 272 m_outstanding_count++; 273 } else { 274 // There is an outstanding read request for the cache line 275 m_load_waiting_on_load++; 276 return RequestStatus_Aliased; 277 } 278 } 279 280 m_outstandReqHist.sample(m_outstanding_count); 281 assert(m_outstanding_count == 282 (m_writeRequestTable.size() + m_readRequestTable.size())); 283 284 return RequestStatus_Ready; 285} 286 287void 288Sequencer::markRemoved() 289{ 290 m_outstanding_count--; 291 assert(m_outstanding_count == 292 m_writeRequestTable.size() + m_readRequestTable.size()); 293} 294 295void 296Sequencer::removeRequest(SequencerRequest* srequest) 297{ 298 assert(m_outstanding_count == 299 m_writeRequestTable.size() + m_readRequestTable.size()); 300 301 Addr line_addr = makeLineAddress(srequest->pkt->getAddr()); 302 if ((srequest->m_type == RubyRequestType_ST) || 303 (srequest->m_type == RubyRequestType_RMW_Read) || 304 (srequest->m_type == RubyRequestType_RMW_Write) || 305 (srequest->m_type == RubyRequestType_Load_Linked) || 306 (srequest->m_type == RubyRequestType_Store_Conditional) || 307 (srequest->m_type == RubyRequestType_Locked_RMW_Read) || 308 (srequest->m_type == RubyRequestType_Locked_RMW_Write)) { 309 m_writeRequestTable.erase(line_addr); 310 } else { 311 m_readRequestTable.erase(line_addr); 312 } 313 314 markRemoved(); 315} 316 317void 318Sequencer::invalidateSC(Addr address) 319{ 320 RequestTable::iterator i = m_writeRequestTable.find(address); 321 if (i != m_writeRequestTable.end()) { 322 SequencerRequest* request = i->second; 323 // The controller has lost the coherence permissions, hence the lock 324 // on the cache line maintained by the cache should be cleared. 325 if (request->m_type == RubyRequestType_Store_Conditional) { 326 m_dataCache_ptr->clearLocked(address); 327 } 328 } 329} 330 331bool 332Sequencer::handleLlsc(Addr address, SequencerRequest* request) 333{ 334 // 335 // The success flag indicates whether the LLSC operation was successful. 336 // LL ops will always succeed, but SC may fail if the cache line is no 337 // longer locked. 338 // 339 bool success = true; 340 if (request->m_type == RubyRequestType_Store_Conditional) { 341 if (!m_dataCache_ptr->isLocked(address, m_version)) { 342 // 343 // For failed SC requests, indicate the failure to the cpu by 344 // setting the extra data to zero. 345 // 346 request->pkt->req->setExtraData(0); 347 success = false; 348 } else { 349 // 350 // For successful SC requests, indicate the success to the cpu by 351 // setting the extra data to one. 352 // 353 request->pkt->req->setExtraData(1); 354 } 355 // 356 // Independent of success, all SC operations must clear the lock 357 // 358 m_dataCache_ptr->clearLocked(address); 359 } else if (request->m_type == RubyRequestType_Load_Linked) { 360 // 361 // Note: To fully follow Alpha LLSC semantics, should the LL clear any 362 // previously locked cache lines? 363 // 364 m_dataCache_ptr->setLocked(address, m_version); 365 } else if ((m_dataCache_ptr->isTagPresent(address)) && 366 (m_dataCache_ptr->isLocked(address, m_version))) { 367 // 368 // Normal writes should clear the locked address 369 // 370 m_dataCache_ptr->clearLocked(address); 371 } 372 return success; 373} 374 375void 376Sequencer::recordMissLatency(const Cycles cycles, const RubyRequestType type, 377 const MachineType respondingMach, 378 bool isExternalHit, Cycles issuedTime, 379 Cycles initialRequestTime, 380 Cycles forwardRequestTime, 381 Cycles firstResponseTime, Cycles completionTime) 382{ 383 m_latencyHist.sample(cycles); 384 m_typeLatencyHist[type]->sample(cycles); 385 386 if (isExternalHit) { 387 m_missLatencyHist.sample(cycles); 388 m_missTypeLatencyHist[type]->sample(cycles); 389 390 if (respondingMach != MachineType_NUM) { 391 m_missMachLatencyHist[respondingMach]->sample(cycles); 392 m_missTypeMachLatencyHist[type][respondingMach]->sample(cycles); 393 394 if ((issuedTime <= initialRequestTime) && 395 (initialRequestTime <= forwardRequestTime) && 396 (forwardRequestTime <= firstResponseTime) && 397 (firstResponseTime <= completionTime)) { 398 399 m_IssueToInitialDelayHist[respondingMach]->sample( 400 initialRequestTime - issuedTime); 401 m_InitialToForwardDelayHist[respondingMach]->sample( 402 forwardRequestTime - initialRequestTime); 403 m_ForwardToFirstResponseDelayHist[respondingMach]->sample( 404 firstResponseTime - forwardRequestTime); 405 m_FirstResponseToCompletionDelayHist[respondingMach]->sample( 406 completionTime - firstResponseTime); 407 } else { 408 m_IncompleteTimes[respondingMach]++; 409 } 410 } 411 } else { 412 m_hitLatencyHist.sample(cycles); 413 m_hitTypeLatencyHist[type]->sample(cycles); 414 415 if (respondingMach != MachineType_NUM) { 416 m_hitMachLatencyHist[respondingMach]->sample(cycles); 417 m_hitTypeMachLatencyHist[type][respondingMach]->sample(cycles); 418 } 419 } 420} 421 422void 423Sequencer::writeCallback(Addr address, DataBlock& data, 424 const bool externalHit, const MachineType mach, 425 const Cycles initialRequestTime, 426 const Cycles forwardRequestTime, 427 const Cycles firstResponseTime) 428{ 429 assert(address == makeLineAddress(address)); 430 assert(m_writeRequestTable.count(makeLineAddress(address))); 431 432 RequestTable::iterator i = m_writeRequestTable.find(address); 433 assert(i != m_writeRequestTable.end()); 434 SequencerRequest* request = i->second; 435 436 m_writeRequestTable.erase(i); 437 markRemoved(); 438 439 assert((request->m_type == RubyRequestType_ST) || 440 (request->m_type == RubyRequestType_ATOMIC) || 441 (request->m_type == RubyRequestType_RMW_Read) || 442 (request->m_type == RubyRequestType_RMW_Write) || 443 (request->m_type == RubyRequestType_Load_Linked) || 444 (request->m_type == RubyRequestType_Store_Conditional) || 445 (request->m_type == RubyRequestType_Locked_RMW_Read) || 446 (request->m_type == RubyRequestType_Locked_RMW_Write) || 447 (request->m_type == RubyRequestType_FLUSH)); 448 449 // 450 // For Alpha, properly handle LL, SC, and write requests with respect to 451 // locked cache blocks. 452 // 453 // Not valid for Network_test protocl 454 // 455 bool success = true; 456 if(!m_usingNetworkTester) 457 success = handleLlsc(address, request); 458 459 if (request->m_type == RubyRequestType_Locked_RMW_Read) { 460 m_controller->blockOnQueue(address, m_mandatory_q_ptr); 461 } else if (request->m_type == RubyRequestType_Locked_RMW_Write) { 462 m_controller->unblock(address); 463 } 464 465 hitCallback(request, data, success, mach, externalHit, 466 initialRequestTime, forwardRequestTime, firstResponseTime); 467} 468 469void 470Sequencer::readCallback(Addr address, DataBlock& data, 471 bool externalHit, const MachineType mach, 472 Cycles initialRequestTime, 473 Cycles forwardRequestTime, 474 Cycles firstResponseTime) 475{ 476 assert(address == makeLineAddress(address)); 477 assert(m_readRequestTable.count(makeLineAddress(address))); 478 479 RequestTable::iterator i = m_readRequestTable.find(address); 480 assert(i != m_readRequestTable.end()); 481 SequencerRequest* request = i->second; 482 483 m_readRequestTable.erase(i); 484 markRemoved(); 485 486 assert((request->m_type == RubyRequestType_LD) || 487 (request->m_type == RubyRequestType_IFETCH)); 488 489 hitCallback(request, data, true, mach, externalHit, 490 initialRequestTime, forwardRequestTime, firstResponseTime); 491} 492 493void 494Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data, 495 bool llscSuccess, 496 const MachineType mach, const bool externalHit, 497 const Cycles initialRequestTime, 498 const Cycles forwardRequestTime, 499 const Cycles firstResponseTime) 500{ 501 PacketPtr pkt = srequest->pkt; 502 Addr request_address(pkt->getAddr()); 503 Addr request_line_address = makeLineAddress(pkt->getAddr()); 504 RubyRequestType type = srequest->m_type; 505 Cycles issued_time = srequest->issue_time; 506 507 // Set this cache entry to the most recently used 508 if (type == RubyRequestType_IFETCH) { 509 m_instCache_ptr->setMRU(request_line_address); 510 } else { 511 m_dataCache_ptr->setMRU(request_line_address); 512 } 513 514 assert(curCycle() >= issued_time); 515 Cycles total_latency = curCycle() - issued_time; 516 517 // Profile the latency for all demand accesses. 518 recordMissLatency(total_latency, type, mach, externalHit, issued_time, 519 initialRequestTime, forwardRequestTime, 520 firstResponseTime, curCycle()); 521 522 DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %d cycles\n", 523 curTick(), m_version, "Seq", 524 llscSuccess ? "Done" : "SC_Failed", "", "", 525 request_address, total_latency); 526 527 // update the data unless it is a non-data-carrying flush 528 if (RubySystem::getWarmupEnabled()) { 529 data.setData(pkt->getConstPtr<uint8_t>(), 530 getOffset(request_address), pkt->getSize()); 531 } else if (!pkt->isFlush()) { 532 if ((type == RubyRequestType_LD) || 533 (type == RubyRequestType_IFETCH) || 534 (type == RubyRequestType_RMW_Read) || 535 (type == RubyRequestType_Locked_RMW_Read) || 536 (type == RubyRequestType_Load_Linked)) { 537 memcpy(pkt->getPtr<uint8_t>(), 538 data.getData(getOffset(request_address), pkt->getSize()), 539 pkt->getSize()); 540 DPRINTF(RubySequencer, "read data %s\n", data); 541 } else { 542 data.setData(pkt->getConstPtr<uint8_t>(), 543 getOffset(request_address), pkt->getSize()); 544 DPRINTF(RubySequencer, "set data %s\n", data); 545 } 546 } 547 548 // If using the RubyTester, update the RubyTester sender state's 549 // subBlock with the recieved data. The tester will later access 550 // this state. 551 if (m_usingRubyTester) { 552 DPRINTF(RubySequencer, "hitCallback %s 0x%x using RubyTester\n", 553 pkt->cmdString(), pkt->getAddr()); 554 RubyTester::SenderState* testerSenderState = 555 pkt->findNextSenderState<RubyTester::SenderState>(); 556 assert(testerSenderState); 557 testerSenderState->subBlock.mergeFrom(data); 558 } 559 560 delete srequest; 561 562 RubySystem *rs = m_ruby_system; 563 if (RubySystem::getWarmupEnabled()) { 564 assert(pkt->req); 565 delete pkt->req; 566 delete pkt; 567 rs->m_cache_recorder->enqueueNextFetchRequest(); 568 } else if (RubySystem::getCooldownEnabled()) { 569 delete pkt; 570 rs->m_cache_recorder->enqueueNextFlushRequest(); 571 } else { 572 ruby_hit_callback(pkt); 573 } 574} 575 576bool 577Sequencer::empty() const 578{ 579 return m_writeRequestTable.empty() && m_readRequestTable.empty(); 580} 581 582RequestStatus 583Sequencer::makeRequest(PacketPtr pkt) 584{ 585 if (m_outstanding_count >= m_max_outstanding_requests) { 586 return RequestStatus_BufferFull; 587 } 588 589 RubyRequestType primary_type = RubyRequestType_NULL; 590 RubyRequestType secondary_type = RubyRequestType_NULL; 591 592 if (pkt->isLLSC()) { 593 // 594 // Alpha LL/SC instructions need to be handled carefully by the cache 595 // coherence protocol to ensure they follow the proper semantics. In 596 // particular, by identifying the operations as atomic, the protocol 597 // should understand that migratory sharing optimizations should not 598 // be performed (i.e. a load between the LL and SC should not steal 599 // away exclusive permission). 600 // 601 if (pkt->isWrite()) { 602 DPRINTF(RubySequencer, "Issuing SC\n"); 603 primary_type = RubyRequestType_Store_Conditional; 604 } else { 605 DPRINTF(RubySequencer, "Issuing LL\n"); 606 assert(pkt->isRead()); 607 primary_type = RubyRequestType_Load_Linked; 608 } 609 secondary_type = RubyRequestType_ATOMIC; 610 } else if (pkt->req->isLockedRMW()) { 611 // 612 // x86 locked instructions are translated to store cache coherence 613 // requests because these requests should always be treated as read 614 // exclusive operations and should leverage any migratory sharing 615 // optimization built into the protocol. 616 // 617 if (pkt->isWrite()) { 618 DPRINTF(RubySequencer, "Issuing Locked RMW Write\n"); 619 primary_type = RubyRequestType_Locked_RMW_Write; 620 } else { 621 DPRINTF(RubySequencer, "Issuing Locked RMW Read\n"); 622 assert(pkt->isRead()); 623 primary_type = RubyRequestType_Locked_RMW_Read; 624 } 625 secondary_type = RubyRequestType_ST; 626 } else { 627 if (pkt->isRead()) { 628 if (pkt->req->isInstFetch()) { 629 primary_type = secondary_type = RubyRequestType_IFETCH; 630 } else { 631 bool storeCheck = false; 632 // only X86 need the store check 633 if (system->getArch() == Arch::X86ISA) { 634 uint32_t flags = pkt->req->getFlags(); 635 storeCheck = flags & 636 (X86ISA::StoreCheck << X86ISA::FlagShift); 637 } 638 if (storeCheck) { 639 primary_type = RubyRequestType_RMW_Read; 640 secondary_type = RubyRequestType_ST; 641 } else { 642 primary_type = secondary_type = RubyRequestType_LD; 643 } 644 } 645 } else if (pkt->isWrite()) { 646 // 647 // Note: M5 packets do not differentiate ST from RMW_Write 648 // 649 primary_type = secondary_type = RubyRequestType_ST; 650 } else if (pkt->isFlush()) { 651 primary_type = secondary_type = RubyRequestType_FLUSH; 652 } else { 653 panic("Unsupported ruby packet type\n"); 654 } 655 } 656 657 RequestStatus status = insertRequest(pkt, primary_type); 658 if (status != RequestStatus_Ready) 659 return status; 660 661 issueRequest(pkt, secondary_type); 662 663 // TODO: issue hardware prefetches here 664 return RequestStatus_Issued; 665} 666 667void 668Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type) 669{ 670 assert(pkt != NULL); 671 ContextID proc_id = pkt->req->hasContextId() ? 672 pkt->req->contextId() : InvalidContextID; 673 674 // If valid, copy the pc to the ruby request 675 Addr pc = 0; 676 if (pkt->req->hasPC()) { 677 pc = pkt->req->getPC(); 678 } 679 680 // check if the packet has data as for example prefetch and flush 681 // requests do not 682 std::shared_ptr<RubyRequest> msg = 683 std::make_shared<RubyRequest>(clockEdge(), pkt->getAddr(), 684 pkt->isFlush() ? 685 nullptr : pkt->getPtr<uint8_t>(), 686 pkt->getSize(), pc, secondary_type, 687 RubyAccessMode_Supervisor, pkt, 688 PrefetchBit_No, proc_id); 689 690 DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %s\n", 691 curTick(), m_version, "Seq", "Begin", "", "", 692 msg->getPhysicalAddress(), 693 RubyRequestType_to_string(secondary_type)); 694 695 // The Sequencer currently assesses instruction and data cache hit latency 696 // for the top-level caches at the beginning of a memory access. 697 // TODO: Eventually, this latency should be moved to represent the actual 698 // cache access latency portion of the memory access. This will require 699 // changing cache controller protocol files to assess the latency on the 700 // access response path. 701 Cycles latency(0); // Initialize to zero to catch misconfigured latency 702 if (secondary_type == RubyRequestType_IFETCH) 703 latency = m_inst_cache_hit_latency; 704 else 705 latency = m_data_cache_hit_latency; 706 707 // Send the message to the cache controller 708 assert(latency > 0); 709 710 assert(m_mandatory_q_ptr != NULL); 711 m_mandatory_q_ptr->enqueue(msg, latency); 712} 713 714template <class KEY, class VALUE> 715std::ostream & 716operator<<(ostream &out, const m5::hash_map<KEY, VALUE> &map) 717{ 718 typename m5::hash_map<KEY, VALUE>::const_iterator i = map.begin(); 719 typename m5::hash_map<KEY, VALUE>::const_iterator end = map.end(); 720 721 out << "["; 722 for (; i != end; ++i) 723 out << " " << i->first << "=" << i->second; 724 out << " ]"; 725 726 return out; 727} 728 729void 730Sequencer::print(ostream& out) const 731{ 732 out << "[Sequencer: " << m_version 733 << ", outstanding requests: " << m_outstanding_count 734 << ", read request table: " << m_readRequestTable 735 << ", write request table: " << m_writeRequestTable 736 << "]"; 737} 738 739// this can be called from setState whenever coherence permissions are 740// upgraded when invoked, coherence violations will be checked for the 741// given block 742void 743Sequencer::checkCoherence(Addr addr) 744{ 745#ifdef CHECK_COHERENCE 746 m_ruby_system->checkGlobalCoherenceInvariant(addr); 747#endif 748} 749 750void 751Sequencer::recordRequestType(SequencerRequestType requestType) { 752 DPRINTF(RubyStats, "Recorded statistic: %s\n", 753 SequencerRequestType_to_string(requestType)); 754} 755 756 757void 758Sequencer::evictionCallback(Addr address) 759{ 760 ruby_eviction_callback(address); 761} 762 763void 764Sequencer::regStats() 765{ 766 m_store_waiting_on_load 767 .name(name() + ".store_waiting_on_load") 768 .desc("Number of times a store aliased with a pending load") 769 .flags(Stats::nozero); 770 m_store_waiting_on_store 771 .name(name() + ".store_waiting_on_store") 772 .desc("Number of times a store aliased with a pending store") 773 .flags(Stats::nozero); 774 m_load_waiting_on_load 775 .name(name() + ".load_waiting_on_load") 776 .desc("Number of times a load aliased with a pending load") 777 .flags(Stats::nozero); 778 m_load_waiting_on_store 779 .name(name() + ".load_waiting_on_store") 780 .desc("Number of times a load aliased with a pending store") 781 .flags(Stats::nozero); 782 783 // These statistical variables are not for display. 784 // The profiler will collate these across different 785 // sequencers and display those collated statistics. 786 m_outstandReqHist.init(10); 787 m_latencyHist.init(10); 788 m_hitLatencyHist.init(10); 789 m_missLatencyHist.init(10); 790 791 for (int i = 0; i < RubyRequestType_NUM; i++) { 792 m_typeLatencyHist.push_back(new Stats::Histogram()); 793 m_typeLatencyHist[i]->init(10); 794 795 m_hitTypeLatencyHist.push_back(new Stats::Histogram()); 796 m_hitTypeLatencyHist[i]->init(10); 797 798 m_missTypeLatencyHist.push_back(new Stats::Histogram()); 799 m_missTypeLatencyHist[i]->init(10); 800 } 801 802 for (int i = 0; i < MachineType_NUM; i++) { 803 m_hitMachLatencyHist.push_back(new Stats::Histogram()); 804 m_hitMachLatencyHist[i]->init(10); 805 806 m_missMachLatencyHist.push_back(new Stats::Histogram()); 807 m_missMachLatencyHist[i]->init(10); 808 809 m_IssueToInitialDelayHist.push_back(new Stats::Histogram()); 810 m_IssueToInitialDelayHist[i]->init(10); 811 812 m_InitialToForwardDelayHist.push_back(new Stats::Histogram()); 813 m_InitialToForwardDelayHist[i]->init(10); 814 815 m_ForwardToFirstResponseDelayHist.push_back(new Stats::Histogram()); 816 m_ForwardToFirstResponseDelayHist[i]->init(10); 817 818 m_FirstResponseToCompletionDelayHist.push_back(new Stats::Histogram()); 819 m_FirstResponseToCompletionDelayHist[i]->init(10); 820 } 821 822 for (int i = 0; i < RubyRequestType_NUM; i++) { 823 m_hitTypeMachLatencyHist.push_back(std::vector<Stats::Histogram *>()); 824 m_missTypeMachLatencyHist.push_back(std::vector<Stats::Histogram *>()); 825 826 for (int j = 0; j < MachineType_NUM; j++) { 827 m_hitTypeMachLatencyHist[i].push_back(new Stats::Histogram()); 828 m_hitTypeMachLatencyHist[i][j]->init(10); 829 830 m_missTypeMachLatencyHist[i].push_back(new Stats::Histogram()); 831 m_missTypeMachLatencyHist[i][j]->init(10); 832 } 833 } 834} 835