Sequencer.cc revision 9773
12SN/A/* 21762SN/A * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 37778Sgblack@eecs.umich.edu * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272SN/A */ 282665Ssaidi@eecs.umich.edu 292665Ssaidi@eecs.umich.edu#include "base/misc.hh" 302665Ssaidi@eecs.umich.edu#include "base/str.hh" 317778Sgblack@eecs.umich.edu#include "config/the_isa.hh" 322SN/A#if THE_ISA == X86_ISA 332SN/A#include "arch/x86/insts/microldstop.hh" 341078SN/A#endif // X86_ISA 351078SN/A#include "cpu/testers/rubytest/RubyTester.hh" 361078SN/A#include "debug/MemoryAccess.hh" 371114SN/A#include "debug/ProtocolTrace.hh" 381078SN/A#include "debug/RubySequencer.hh" 391114SN/A#include "debug/RubyStats.hh" 401114SN/A#include "mem/protocol/PrefetchBit.hh" 411114SN/A#include "mem/protocol/RubyAccessMode.hh" 421114SN/A#include "mem/ruby/common/Global.hh" 436216Snate@binkert.org#include "mem/ruby/profiler/Profiler.hh" 441114SN/A#include "mem/ruby/slicc_interface/RubyRequest.hh" 451078SN/A#include "mem/ruby/system/Sequencer.hh" 461078SN/A#include "mem/ruby/system/System.hh" 471078SN/A#include "mem/packet.hh" 481078SN/A 491078SN/Ausing namespace std; 501078SN/A 511078SN/ASequencer * 521078SN/ARubySequencerParams::create() 531078SN/A{ 541078SN/A return new Sequencer(this); 551078SN/A} 561078SN/A 571078SN/ASequencer::Sequencer(const Params *p) 581078SN/A : RubyPort(p), deadlockCheckEvent(this) 591078SN/A{ 602SN/A m_store_waiting_on_load_cycles = 0; 611114SN/A m_store_waiting_on_store_cycles = 0; 622SN/A m_load_waiting_on_store_cycles = 0; 631114SN/A m_load_waiting_on_load_cycles = 0; 641114SN/A 651114SN/A m_outstanding_count = 0; 661114SN/A 671114SN/A m_instCache_ptr = p->icache; 681114SN/A m_dataCache_ptr = p->dcache; 691114SN/A m_max_outstanding_requests = p->max_outstanding_requests; 701078SN/A m_deadlock_threshold = p->deadlock_threshold; 711114SN/A 721114SN/A assert(m_max_outstanding_requests > 0); 731114SN/A assert(m_deadlock_threshold > 0); 741114SN/A assert(m_instCache_ptr != NULL); 751114SN/A assert(m_dataCache_ptr != NULL); 761114SN/A 771114SN/A m_usingNetworkTester = p->using_network_tester; 781079SN/A} 791114SN/A 801114SN/ASequencer::~Sequencer() 811114SN/A{ 821114SN/A} 831114SN/A 841114SN/Avoid 851114SN/ASequencer::wakeup() 861114SN/A{ 871114SN/A assert(getDrainState() != Drainable::Draining); 881114SN/A 891137SN/A // Check for deadlock of any of the requests 901137SN/A Cycles current_time = curCycle(); 911137SN/A 921137SN/A // Check across all outstanding requests 931137SN/A int total_outstanding = 0; 941137SN/A 951137SN/A RequestTable::iterator read = m_readRequestTable.begin(); 961137SN/A RequestTable::iterator read_end = m_readRequestTable.end(); 971137SN/A for (; read != read_end; ++read) { 981137SN/A SequencerRequest* request = read->second; 991137SN/A if (current_time - request->issue_time < m_deadlock_threshold) 1001137SN/A continue; 1011137SN/A 1021114SN/A panic("Possible Deadlock detected. Aborting!\n" 1031114SN/A "version: %d request.paddr: 0x%x m_readRequestTable: %d " 1041114SN/A "current time: %u issue_time: %d difference: %d\n", m_version, 1051114SN/A Address(request->pkt->getAddr()), m_readRequestTable.size(), 1061114SN/A current_time * clockPeriod(), request->issue_time * clockPeriod(), 1071114SN/A (current_time * clockPeriod()) - (request->issue_time * clockPeriod())); 1081078SN/A } 1091078SN/A 1101114SN/A RequestTable::iterator write = m_writeRequestTable.begin(); 1111114SN/A RequestTable::iterator write_end = m_writeRequestTable.end(); 1121079SN/A for (; write != write_end; ++write) { 1131114SN/A SequencerRequest* request = write->second; 1141079SN/A if (current_time - request->issue_time < m_deadlock_threshold) 1151079SN/A continue; 1161079SN/A 1171079SN/A panic("Possible Deadlock detected. Aborting!\n" 1181079SN/A "version: %d request.paddr: 0x%x m_writeRequestTable: %d " 1191078SN/A "current time: %u issue_time: %d difference: %d\n", m_version, 1201078SN/A Address(request->pkt->getAddr()), m_writeRequestTable.size(), 1211114SN/A current_time * clockPeriod(), request->issue_time * clockPeriod(), 1221114SN/A (current_time * clockPeriod()) - (request->issue_time * clockPeriod())); 1231114SN/A } 1241114SN/A 1252566SN/A total_outstanding += m_writeRequestTable.size(); 1261114SN/A total_outstanding += m_readRequestTable.size(); 1271114SN/A 1281114SN/A assert(m_outstanding_count == total_outstanding); 1292566SN/A 1301114SN/A if (m_outstanding_count > 0) { 1311114SN/A // If there are still outstanding requests, keep checking 1321114SN/A schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold)); 1331114SN/A } 1341114SN/A} 1351114SN/A 1361114SN/Avoid Sequencer::clearStats() 1371114SN/A{ 1381114SN/A m_outstandReqHist.clear(); 1392566SN/A 1401114SN/A // Initialize the histograms that track latency of all requests 1412566SN/A m_latencyHist.clear(20); 1422566SN/A m_typeLatencyHist.resize(RubyRequestType_NUM); 1431114SN/A for (int i = 0; i < RubyRequestType_NUM; i++) { 1441114SN/A m_typeLatencyHist[i].clear(20); 1455782Ssaidi@eecs.umich.edu } 1465782Ssaidi@eecs.umich.edu 1471114SN/A // Initialize the histograms that track latency of requests that 1481114SN/A // hit in the cache attached to the sequencer. 1491114SN/A m_hitLatencyHist.clear(20); 1501114SN/A m_hitTypeLatencyHist.resize(RubyRequestType_NUM); 1511114SN/A m_hitTypeMachLatencyHist.resize(RubyRequestType_NUM); 1527777Sgblack@eecs.umich.edu 1537777Sgblack@eecs.umich.edu for (int i = 0; i < RubyRequestType_NUM; i++) { 1547777Sgblack@eecs.umich.edu m_hitTypeLatencyHist[i].clear(20); 1557777Sgblack@eecs.umich.edu m_hitTypeMachLatencyHist[i].resize(MachineType_NUM); 1567777Sgblack@eecs.umich.edu for (int j = 0; j < MachineType_NUM; j++) { 1577777Sgblack@eecs.umich.edu m_hitTypeMachLatencyHist[i][j].clear(20); 1587777Sgblack@eecs.umich.edu } 1597777Sgblack@eecs.umich.edu } 1607777Sgblack@eecs.umich.edu 1617777Sgblack@eecs.umich.edu // Initialize the histograms that track the latency of requests that 1627777Sgblack@eecs.umich.edu // missed in the cache attached to the sequencer. 1637777Sgblack@eecs.umich.edu m_missLatencyHist.clear(20); 1647777Sgblack@eecs.umich.edu m_missTypeLatencyHist.resize(RubyRequestType_NUM); 1657777Sgblack@eecs.umich.edu m_missTypeMachLatencyHist.resize(RubyRequestType_NUM); 1667777Sgblack@eecs.umich.edu 1677777Sgblack@eecs.umich.edu for (int i = 0; i < RubyRequestType_NUM; i++) { 1687777Sgblack@eecs.umich.edu m_missTypeLatencyHist[i].clear(20); 1697777Sgblack@eecs.umich.edu m_missTypeMachLatencyHist[i].resize(MachineType_NUM); 1707777Sgblack@eecs.umich.edu for (int j = 0; j < MachineType_NUM; j++) { 1717777Sgblack@eecs.umich.edu m_missTypeMachLatencyHist[i][j].clear(20); 1727777Sgblack@eecs.umich.edu } 1737777Sgblack@eecs.umich.edu } 1747777Sgblack@eecs.umich.edu 1757777Sgblack@eecs.umich.edu m_hitMachLatencyHist.resize(MachineType_NUM); 1767777Sgblack@eecs.umich.edu m_missMachLatencyHist.resize(MachineType_NUM); 1777777Sgblack@eecs.umich.edu m_IssueToInitialDelayHist.resize(MachineType_NUM); 1787777Sgblack@eecs.umich.edu m_InitialToForwardDelayHist.resize(MachineType_NUM); 1797777Sgblack@eecs.umich.edu m_ForwardToFirstResponseDelayHist.resize(MachineType_NUM); 1807777Sgblack@eecs.umich.edu m_FirstResponseToCompletionDelayHist.resize(MachineType_NUM); 1817777Sgblack@eecs.umich.edu m_IncompleteTimes.resize(MachineType_NUM); 1827777Sgblack@eecs.umich.edu 1837777Sgblack@eecs.umich.edu for (int i = 0; i < MachineType_NUM; i++) { 1847777Sgblack@eecs.umich.edu m_missMachLatencyHist[i].clear(20); 1857777Sgblack@eecs.umich.edu m_hitMachLatencyHist[i].clear(20); 1867777Sgblack@eecs.umich.edu 1877777Sgblack@eecs.umich.edu m_IssueToInitialDelayHist[i].clear(20); 1887777Sgblack@eecs.umich.edu m_InitialToForwardDelayHist[i].clear(20); 1897777Sgblack@eecs.umich.edu m_ForwardToFirstResponseDelayHist[i].clear(20); 1907777Sgblack@eecs.umich.edu m_FirstResponseToCompletionDelayHist[i].clear(20); 1917777Sgblack@eecs.umich.edu 1927777Sgblack@eecs.umich.edu m_IncompleteTimes[i] = 0; 1937777Sgblack@eecs.umich.edu } 1947777Sgblack@eecs.umich.edu} 1957777Sgblack@eecs.umich.edu 1967777Sgblack@eecs.umich.eduvoid 1977777Sgblack@eecs.umich.eduSequencer::printStats(ostream & out) const 1987777Sgblack@eecs.umich.edu{ 1997777Sgblack@eecs.umich.edu out << "Sequencer: " << m_name << endl 2007777Sgblack@eecs.umich.edu << " store_waiting_on_load_cycles: " 2017777Sgblack@eecs.umich.edu << m_store_waiting_on_load_cycles << endl 2027777Sgblack@eecs.umich.edu << " store_waiting_on_store_cycles: " 2037777Sgblack@eecs.umich.edu << m_store_waiting_on_store_cycles << endl 2047777Sgblack@eecs.umich.edu << " load_waiting_on_load_cycles: " 2057777Sgblack@eecs.umich.edu << m_load_waiting_on_load_cycles << endl 2067777Sgblack@eecs.umich.edu << " load_waiting_on_store_cycles: " 2077777Sgblack@eecs.umich.edu << m_load_waiting_on_store_cycles << endl; 2087777Sgblack@eecs.umich.edu} 2097777Sgblack@eecs.umich.edu 2107777Sgblack@eecs.umich.eduvoid 2111114SN/ASequencer::printProgress(ostream& out) const 2121114SN/A{ 2131078SN/A#if 0 2141078SN/A int total_demand = 0; 2151092SN/A out << "Sequencer Stats Version " << m_version << endl; 2161078SN/A out << "Current time = " << g_system_ptr->getTime() << endl; 2171078SN/A out << "---------------" << endl; 2181078SN/A out << "outstanding requests" << endl; 2191078SN/A 2201078SN/A out << "proc " << m_Read 2211078SN/A << " version Requests = " << m_readRequestTable.size() << endl; 2221078SN/A 2231092SN/A // print the request table 2241078SN/A RequestTable::iterator read = m_readRequestTable.begin(); 2251078SN/A RequestTable::iterator read_end = m_readRequestTable.end(); 2261078SN/A for (; read != read_end; ++read) { 2271092SN/A SequencerRequest* request = read->second; 2285761Ssaidi@eecs.umich.edu out << "\tRequest[ " << i << " ] = " << request->type 2295761Ssaidi@eecs.umich.edu << " Address " << rkeys[i] 2305761Ssaidi@eecs.umich.edu << " Posted " << request->issue_time 2311078SN/A << " PF " << PrefetchBit_No << endl; 2321114SN/A total_demand++; 2331079SN/A } 2341079SN/A 2351079SN/A out << "proc " << m_version 2361079SN/A << " Write Requests = " << m_writeRequestTable.size << endl; 2371079SN/A 2381079SN/A // print the request table 2391078SN/A RequestTable::iterator write = m_writeRequestTable.begin(); 2401078SN/A RequestTable::iterator write_end = m_writeRequestTable.end(); 2411114SN/A for (; write != write_end; ++write) { 2421114SN/A SequencerRequest* request = write->second; 2431114SN/A out << "\tRequest[ " << i << " ] = " << request.getType() 2441114SN/A << " Address " << wkeys[i] 2451114SN/A << " Posted " << request.getTime() 2462566SN/A << " PF " << request.getPrefetch() << endl; 2471114SN/A if (request.getPrefetch() == PrefetchBit_No) { 2482566SN/A total_demand++; 2491114SN/A } 2505484Snate@binkert.org } 2515484Snate@binkert.org 2525484Snate@binkert.org out << endl; 2535484Snate@binkert.org 2545484Snate@binkert.org out << "Total Number Outstanding: " << m_outstanding_count << endl 2555484Snate@binkert.org << "Total Number Demand : " << total_demand << endl 2565484Snate@binkert.org << "Total Number Prefetches : " << m_outstanding_count - total_demand 2571114SN/A << endl << endl << endl; 2581114SN/A#endif 2591114SN/A} 2605484Snate@binkert.org 2615484Snate@binkert.org// Insert the request on the correct request table. Return true if 2625484Snate@binkert.org// the entry was already present. 2631114SN/ARequestStatus 2641114SN/ASequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type) 2655484Snate@binkert.org{ 2665484Snate@binkert.org assert(m_outstanding_count == 2675484Snate@binkert.org (m_writeRequestTable.size() + m_readRequestTable.size())); 2681114SN/A 2695484Snate@binkert.org // See if we should schedule a deadlock check 2705484Snate@binkert.org if (!deadlockCheckEvent.scheduled() && 2715484Snate@binkert.org getDrainState() != Drainable::Draining) { 2725484Snate@binkert.org schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold)); 2731114SN/A } 2742566SN/A 2751114SN/A Address line_addr(pkt->getAddr()); 2761114SN/A line_addr.makeLineAddress(); 2771114SN/A // Create a default entry, mapping the address to NULL, the cast is 2782566SN/A // there to make gcc 4.4 happy 2792566SN/A RequestTable::value_type default_entry(line_addr, 2801114SN/A (SequencerRequest*) NULL); 2811114SN/A 2825782Ssaidi@eecs.umich.edu if ((request_type == RubyRequestType_ST) || 2835782Ssaidi@eecs.umich.edu (request_type == RubyRequestType_RMW_Read) || 2841114SN/A (request_type == RubyRequestType_RMW_Write) || 2851114SN/A (request_type == RubyRequestType_Load_Linked) || 2861114SN/A (request_type == RubyRequestType_Store_Conditional) || 2871114SN/A (request_type == RubyRequestType_Locked_RMW_Read) || 2881114SN/A (request_type == RubyRequestType_Locked_RMW_Write) || 2891114SN/A (request_type == RubyRequestType_FLUSH)) { 2901114SN/A 2911114SN/A // Check if there is any outstanding read request for the same 2921114SN/A // cache line. 2931114SN/A if (m_readRequestTable.count(line_addr) > 0) { 2941114SN/A m_store_waiting_on_load_cycles++; 2951114SN/A return RequestStatus_Aliased; 2961114SN/A } 2971114SN/A 2981114SN/A pair<RequestTable::iterator, bool> r = 2991114SN/A m_writeRequestTable.insert(default_entry); 3001114SN/A if (r.second) { 3011114SN/A RequestTable::iterator i = r.first; 3021114SN/A i->second = new SequencerRequest(pkt, request_type, curCycle()); 3031114SN/A m_outstanding_count++; 3041114SN/A } else { 3051114SN/A // There is an outstanding write request for the cache line 3061114SN/A m_store_waiting_on_store_cycles++; 3071114SN/A return RequestStatus_Aliased; 3081114SN/A } 3091114SN/A } else { 3101114SN/A // Check if there is any outstanding write request for the same 3111114SN/A // cache line. 3121114SN/A if (m_writeRequestTable.count(line_addr) > 0) { 3131114SN/A m_load_waiting_on_store_cycles++; 3141114SN/A return RequestStatus_Aliased; 3151114SN/A } 3161114SN/A 3171114SN/A pair<RequestTable::iterator, bool> r = 3181114SN/A m_readRequestTable.insert(default_entry); 3191078SN/A 3201078SN/A if (r.second) { 3211078SN/A RequestTable::iterator i = r.first; 3221078SN/A i->second = new SequencerRequest(pkt, request_type, curCycle()); 3231078SN/A m_outstanding_count++; 3241078SN/A } else { 3251078SN/A // There is an outstanding read request for the cache line 3261078SN/A m_load_waiting_on_load_cycles++; 3271092SN/A return RequestStatus_Aliased; 3281078SN/A } 3291078SN/A } 3301092SN/A 3315761Ssaidi@eecs.umich.edu m_outstandReqHist.add(m_outstanding_count); 3325761Ssaidi@eecs.umich.edu assert(m_outstanding_count == 3331078SN/A (m_writeRequestTable.size() + m_readRequestTable.size())); 3341114SN/A 3351114SN/A return RequestStatus_Ready; 3361079SN/A} 3371079SN/A 3381079SN/Avoid 3391079SN/ASequencer::markRemoved() 3401079SN/A{ 3411078SN/A m_outstanding_count--; 3421078SN/A assert(m_outstanding_count == 3431114SN/A m_writeRequestTable.size() + m_readRequestTable.size()); 3441114SN/A} 3451114SN/A 3462566SN/Avoid 3475782Ssaidi@eecs.umich.eduSequencer::removeRequest(SequencerRequest* srequest) 3481114SN/A{ 3495782Ssaidi@eecs.umich.edu assert(m_outstanding_count == 3501114SN/A m_writeRequestTable.size() + m_readRequestTable.size()); 3511114SN/A 3525484Snate@binkert.org Address line_addr(srequest->pkt->getAddr()); 3531114SN/A line_addr.makeLineAddress(); 3541114SN/A if ((srequest->m_type == RubyRequestType_ST) || 3551114SN/A (srequest->m_type == RubyRequestType_RMW_Read) || 3561114SN/A (srequest->m_type == RubyRequestType_RMW_Write) || 3571114SN/A (srequest->m_type == RubyRequestType_Load_Linked) || 3581114SN/A (srequest->m_type == RubyRequestType_Store_Conditional) || 3595782Ssaidi@eecs.umich.edu (srequest->m_type == RubyRequestType_Locked_RMW_Read) || 3605782Ssaidi@eecs.umich.edu (srequest->m_type == RubyRequestType_Locked_RMW_Write)) { 3615782Ssaidi@eecs.umich.edu m_writeRequestTable.erase(line_addr); 3621114SN/A } else { 3635782Ssaidi@eecs.umich.edu m_readRequestTable.erase(line_addr); 3645484Snate@binkert.org } 3655484Snate@binkert.org 3661114SN/A markRemoved(); 3675782Ssaidi@eecs.umich.edu} 3685484Snate@binkert.org 3695484Snate@binkert.orgvoid 3701114SN/ASequencer::invalidateSC(const Address& address) 3711114SN/A{ 3725782Ssaidi@eecs.umich.edu RequestTable::iterator i = m_writeRequestTable.find(address); 3731114SN/A if (i != m_writeRequestTable.end()) { 3742566SN/A SequencerRequest* request = i->second; 3752566SN/A // The controller has lost the coherence permissions, hence the lock 3761114SN/A // on the cache line maintained by the cache should be cleared. 3771114SN/A if (request->m_type == RubyRequestType_Store_Conditional) { 3785782Ssaidi@eecs.umich.edu m_dataCache_ptr->clearLocked(address); 3795782Ssaidi@eecs.umich.edu } 3801114SN/A } 3811114SN/A} 3821114SN/A 3831114SN/Abool 3841114SN/ASequencer::handleLlsc(const Address& address, SequencerRequest* request) 3851114SN/A{ 3861114SN/A // 3871114SN/A // The success flag indicates whether the LLSC operation was successful. 3881114SN/A // LL ops will always succeed, but SC may fail if the cache line is no 3891114SN/A // longer locked. 3901114SN/A // 3911114SN/A bool success = true; 3921114SN/A if (request->m_type == RubyRequestType_Store_Conditional) { 3931114SN/A if (!m_dataCache_ptr->isLocked(address, m_version)) { 3941114SN/A // 3951114SN/A // For failed SC requests, indicate the failure to the cpu by 3961114SN/A // setting the extra data to zero. 3971114SN/A // 3981114SN/A request->pkt->req->setExtraData(0); 3991114SN/A success = false; 4001114SN/A } else { 4011114SN/A // 4021114SN/A // For successful SC requests, indicate the success to the cpu by 4031114SN/A // setting the extra data to one. 4041114SN/A // 4051114SN/A request->pkt->req->setExtraData(1); 4061114SN/A } 4071114SN/A // 4081114SN/A // Independent of success, all SC operations must clear the lock 4091114SN/A // 4101114SN/A m_dataCache_ptr->clearLocked(address); 4111114SN/A } else if (request->m_type == RubyRequestType_Load_Linked) { 4121114SN/A // 4131114SN/A // Note: To fully follow Alpha LLSC semantics, should the LL clear any 4141114SN/A // previously locked cache lines? 4151114SN/A // 4161078SN/A m_dataCache_ptr->setLocked(address, m_version); 4171078SN/A } else if ((m_dataCache_ptr->isTagPresent(address)) && 4181078SN/A (m_dataCache_ptr->isLocked(address, m_version))) { 4191078SN/A // 4201171SN/A // Normal writes should clear the locked address 4211078SN/A // 4221171SN/A m_dataCache_ptr->clearLocked(address); 4235761Ssaidi@eecs.umich.edu } 4241078SN/A return success; 4251114SN/A} 4261079SN/A 4271079SN/Avoid 4281079SN/ASequencer::recordMissLatency(const Cycles cycles, const RubyRequestType type, 4291079SN/A const MachineType respondingMach, 4301078SN/A bool isExternalHit, Cycles issuedTime, 4311078SN/A Cycles initialRequestTime, 4321114SN/A Cycles forwardRequestTime, 4331114SN/A Cycles firstResponseTime, Cycles completionTime) 4341114SN/A{ 4352566SN/A m_latencyHist.add(cycles); 4365782Ssaidi@eecs.umich.edu m_typeLatencyHist[type].add(cycles); 4371114SN/A 4385782Ssaidi@eecs.umich.edu if (isExternalHit) { 4391114SN/A m_missLatencyHist.add(cycles); 4401114SN/A m_missTypeLatencyHist[type].add(cycles); 4415484Snate@binkert.org 4421114SN/A if (respondingMach != MachineType_NUM) { 4431114SN/A m_missMachLatencyHist[respondingMach].add(cycles); 4441114SN/A m_missTypeMachLatencyHist[type][respondingMach].add(cycles); 4451114SN/A 4461114SN/A if ((issuedTime <= initialRequestTime) && 4471114SN/A (initialRequestTime <= forwardRequestTime) && 4485782Ssaidi@eecs.umich.edu (forwardRequestTime <= firstResponseTime) && 4495782Ssaidi@eecs.umich.edu (firstResponseTime <= completionTime)) { 4505782Ssaidi@eecs.umich.edu 4511114SN/A m_IssueToInitialDelayHist[respondingMach].add( 4525782Ssaidi@eecs.umich.edu initialRequestTime - issuedTime); 4535484Snate@binkert.org m_InitialToForwardDelayHist[respondingMach].add( 4545484Snate@binkert.org forwardRequestTime - initialRequestTime); 4551114SN/A m_ForwardToFirstResponseDelayHist[respondingMach].add( 4565782Ssaidi@eecs.umich.edu firstResponseTime - forwardRequestTime); 4575484Snate@binkert.org m_FirstResponseToCompletionDelayHist[respondingMach].add( 4585484Snate@binkert.org completionTime - firstResponseTime); 4591114SN/A } else { 4601114SN/A m_IncompleteTimes[respondingMach]++; 4615782Ssaidi@eecs.umich.edu } 4621114SN/A } 4632566SN/A } else { 4642566SN/A m_hitLatencyHist.add(cycles); 4651114SN/A m_hitTypeLatencyHist[type].add(cycles); 4661114SN/A 4675782Ssaidi@eecs.umich.edu if (respondingMach != MachineType_NUM) { 4685782Ssaidi@eecs.umich.edu m_hitMachLatencyHist[respondingMach].add(cycles); 4691114SN/A m_hitTypeMachLatencyHist[type][respondingMach].add(cycles); 4701114SN/A } 4711114SN/A } 4721114SN/A} 4735782Ssaidi@eecs.umich.edu 4745782Ssaidi@eecs.umich.eduvoid 4751114SN/ASequencer::writeCallback(const Address& address, DataBlock& data, 4761114SN/A const bool externalHit, const MachineType mach, 4771078SN/A const Cycles initialRequestTime, 478 const Cycles forwardRequestTime, 479 const Cycles firstResponseTime) 480{ 481 assert(address == line_address(address)); 482 assert(m_writeRequestTable.count(line_address(address))); 483 484 RequestTable::iterator i = m_writeRequestTable.find(address); 485 assert(i != m_writeRequestTable.end()); 486 SequencerRequest* request = i->second; 487 488 m_writeRequestTable.erase(i); 489 markRemoved(); 490 491 assert((request->m_type == RubyRequestType_ST) || 492 (request->m_type == RubyRequestType_ATOMIC) || 493 (request->m_type == RubyRequestType_RMW_Read) || 494 (request->m_type == RubyRequestType_RMW_Write) || 495 (request->m_type == RubyRequestType_Load_Linked) || 496 (request->m_type == RubyRequestType_Store_Conditional) || 497 (request->m_type == RubyRequestType_Locked_RMW_Read) || 498 (request->m_type == RubyRequestType_Locked_RMW_Write) || 499 (request->m_type == RubyRequestType_FLUSH)); 500 501 // 502 // For Alpha, properly handle LL, SC, and write requests with respect to 503 // locked cache blocks. 504 // 505 // Not valid for Network_test protocl 506 // 507 bool success = true; 508 if(!m_usingNetworkTester) 509 success = handleLlsc(address, request); 510 511 if (request->m_type == RubyRequestType_Locked_RMW_Read) { 512 m_controller->blockOnQueue(address, m_mandatory_q_ptr); 513 } else if (request->m_type == RubyRequestType_Locked_RMW_Write) { 514 m_controller->unblock(address); 515 } 516 517 hitCallback(request, data, success, mach, externalHit, 518 initialRequestTime, forwardRequestTime, firstResponseTime); 519} 520 521void 522Sequencer::readCallback(const Address& address, DataBlock& data, 523 bool externalHit, const MachineType mach, 524 Cycles initialRequestTime, 525 Cycles forwardRequestTime, 526 Cycles firstResponseTime) 527{ 528 assert(address == line_address(address)); 529 assert(m_readRequestTable.count(line_address(address))); 530 531 RequestTable::iterator i = m_readRequestTable.find(address); 532 assert(i != m_readRequestTable.end()); 533 SequencerRequest* request = i->second; 534 535 m_readRequestTable.erase(i); 536 markRemoved(); 537 538 assert((request->m_type == RubyRequestType_LD) || 539 (request->m_type == RubyRequestType_IFETCH)); 540 541 hitCallback(request, data, true, mach, externalHit, 542 initialRequestTime, forwardRequestTime, firstResponseTime); 543} 544 545void 546Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data, 547 bool llscSuccess, 548 const MachineType mach, const bool externalHit, 549 const Cycles initialRequestTime, 550 const Cycles forwardRequestTime, 551 const Cycles firstResponseTime) 552{ 553 PacketPtr pkt = srequest->pkt; 554 Address request_address(pkt->getAddr()); 555 Address request_line_address(pkt->getAddr()); 556 request_line_address.makeLineAddress(); 557 RubyRequestType type = srequest->m_type; 558 Cycles issued_time = srequest->issue_time; 559 560 // Set this cache entry to the most recently used 561 if (type == RubyRequestType_IFETCH) { 562 m_instCache_ptr->setMRU(request_line_address); 563 } else { 564 m_dataCache_ptr->setMRU(request_line_address); 565 } 566 567 assert(curCycle() >= issued_time); 568 Cycles total_latency = curCycle() - issued_time; 569 570 // Profile the latency for all demand accesses. 571 recordMissLatency(total_latency, type, mach, externalHit, issued_time, 572 initialRequestTime, forwardRequestTime, 573 firstResponseTime, curCycle()); 574 575 DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %d cycles\n", 576 curTick(), m_version, "Seq", 577 llscSuccess ? "Done" : "SC_Failed", "", "", 578 request_address, total_latency); 579 580 // update the data 581 if (g_system_ptr->m_warmup_enabled) { 582 assert(pkt->getPtr<uint8_t>(false) != NULL); 583 data.setData(pkt->getPtr<uint8_t>(false), 584 request_address.getOffset(), pkt->getSize()); 585 } else if (pkt->getPtr<uint8_t>(true) != NULL) { 586 if ((type == RubyRequestType_LD) || 587 (type == RubyRequestType_IFETCH) || 588 (type == RubyRequestType_RMW_Read) || 589 (type == RubyRequestType_Locked_RMW_Read) || 590 (type == RubyRequestType_Load_Linked)) { 591 memcpy(pkt->getPtr<uint8_t>(true), 592 data.getData(request_address.getOffset(), pkt->getSize()), 593 pkt->getSize()); 594 } else { 595 data.setData(pkt->getPtr<uint8_t>(true), 596 request_address.getOffset(), pkt->getSize()); 597 } 598 } else { 599 DPRINTF(MemoryAccess, 600 "WARNING. Data not transfered from Ruby to M5 for type %s\n", 601 RubyRequestType_to_string(type)); 602 } 603 604 // If using the RubyTester, update the RubyTester sender state's 605 // subBlock with the recieved data. The tester will later access 606 // this state. 607 // Note: RubyPort will access it's sender state before the 608 // RubyTester. 609 if (m_usingRubyTester) { 610 RubyPort::SenderState *reqSenderState = 611 safe_cast<RubyPort::SenderState*>(pkt->senderState); 612 // @todo This is a dangerous assumption on nothing else 613 // modifying the senderState 614 RubyTester::SenderState* testerSenderState = 615 safe_cast<RubyTester::SenderState*>(reqSenderState->predecessor); 616 testerSenderState->subBlock.mergeFrom(data); 617 } 618 619 delete srequest; 620 621 if (g_system_ptr->m_warmup_enabled) { 622 assert(pkt->req); 623 delete pkt->req; 624 delete pkt; 625 g_system_ptr->m_cache_recorder->enqueueNextFetchRequest(); 626 } else if (g_system_ptr->m_cooldown_enabled) { 627 delete pkt; 628 g_system_ptr->m_cache_recorder->enqueueNextFlushRequest(); 629 } else { 630 ruby_hit_callback(pkt); 631 } 632} 633 634bool 635Sequencer::empty() const 636{ 637 return m_writeRequestTable.empty() && m_readRequestTable.empty(); 638} 639 640RequestStatus 641Sequencer::makeRequest(PacketPtr pkt) 642{ 643 if (m_outstanding_count >= m_max_outstanding_requests) { 644 return RequestStatus_BufferFull; 645 } 646 647 RubyRequestType primary_type = RubyRequestType_NULL; 648 RubyRequestType secondary_type = RubyRequestType_NULL; 649 650 if (pkt->isLLSC()) { 651 // 652 // Alpha LL/SC instructions need to be handled carefully by the cache 653 // coherence protocol to ensure they follow the proper semantics. In 654 // particular, by identifying the operations as atomic, the protocol 655 // should understand that migratory sharing optimizations should not 656 // be performed (i.e. a load between the LL and SC should not steal 657 // away exclusive permission). 658 // 659 if (pkt->isWrite()) { 660 DPRINTF(RubySequencer, "Issuing SC\n"); 661 primary_type = RubyRequestType_Store_Conditional; 662 } else { 663 DPRINTF(RubySequencer, "Issuing LL\n"); 664 assert(pkt->isRead()); 665 primary_type = RubyRequestType_Load_Linked; 666 } 667 secondary_type = RubyRequestType_ATOMIC; 668 } else if (pkt->req->isLocked()) { 669 // 670 // x86 locked instructions are translated to store cache coherence 671 // requests because these requests should always be treated as read 672 // exclusive operations and should leverage any migratory sharing 673 // optimization built into the protocol. 674 // 675 if (pkt->isWrite()) { 676 DPRINTF(RubySequencer, "Issuing Locked RMW Write\n"); 677 primary_type = RubyRequestType_Locked_RMW_Write; 678 } else { 679 DPRINTF(RubySequencer, "Issuing Locked RMW Read\n"); 680 assert(pkt->isRead()); 681 primary_type = RubyRequestType_Locked_RMW_Read; 682 } 683 secondary_type = RubyRequestType_ST; 684 } else { 685 if (pkt->isRead()) { 686 if (pkt->req->isInstFetch()) { 687 primary_type = secondary_type = RubyRequestType_IFETCH; 688 } else { 689#if THE_ISA == X86_ISA 690 uint32_t flags = pkt->req->getFlags(); 691 bool storeCheck = flags & 692 (TheISA::StoreCheck << TheISA::FlagShift); 693#else 694 bool storeCheck = false; 695#endif // X86_ISA 696 if (storeCheck) { 697 primary_type = RubyRequestType_RMW_Read; 698 secondary_type = RubyRequestType_ST; 699 } else { 700 primary_type = secondary_type = RubyRequestType_LD; 701 } 702 } 703 } else if (pkt->isWrite()) { 704 // 705 // Note: M5 packets do not differentiate ST from RMW_Write 706 // 707 primary_type = secondary_type = RubyRequestType_ST; 708 } else if (pkt->isFlush()) { 709 primary_type = secondary_type = RubyRequestType_FLUSH; 710 } else { 711 panic("Unsupported ruby packet type\n"); 712 } 713 } 714 715 RequestStatus status = insertRequest(pkt, primary_type); 716 if (status != RequestStatus_Ready) 717 return status; 718 719 issueRequest(pkt, secondary_type); 720 721 // TODO: issue hardware prefetches here 722 return RequestStatus_Issued; 723} 724 725void 726Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type) 727{ 728 assert(pkt != NULL); 729 int proc_id = -1; 730 if (pkt->req->hasContextId()) { 731 proc_id = pkt->req->contextId(); 732 } 733 734 // If valid, copy the pc to the ruby request 735 Addr pc = 0; 736 if (pkt->req->hasPC()) { 737 pc = pkt->req->getPC(); 738 } 739 740 RubyRequest *msg = new RubyRequest(clockEdge(), pkt->getAddr(), 741 pkt->getPtr<uint8_t>(true), 742 pkt->getSize(), pc, secondary_type, 743 RubyAccessMode_Supervisor, pkt, 744 PrefetchBit_No, proc_id); 745 746 DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %s\n", 747 curTick(), m_version, "Seq", "Begin", "", "", 748 msg->getPhysicalAddress(), 749 RubyRequestType_to_string(secondary_type)); 750 751 Cycles latency(0); // initialzed to an null value 752 753 if (secondary_type == RubyRequestType_IFETCH) 754 latency = m_instCache_ptr->getLatency(); 755 else 756 latency = m_dataCache_ptr->getLatency(); 757 758 // Send the message to the cache controller 759 assert(latency > 0); 760 761 assert(m_mandatory_q_ptr != NULL); 762 m_mandatory_q_ptr->enqueue(msg, latency); 763} 764 765template <class KEY, class VALUE> 766std::ostream & 767operator<<(ostream &out, const m5::hash_map<KEY, VALUE> &map) 768{ 769 typename m5::hash_map<KEY, VALUE>::const_iterator i = map.begin(); 770 typename m5::hash_map<KEY, VALUE>::const_iterator end = map.end(); 771 772 out << "["; 773 for (; i != end; ++i) 774 out << " " << i->first << "=" << i->second; 775 out << " ]"; 776 777 return out; 778} 779 780void 781Sequencer::print(ostream& out) const 782{ 783 out << "[Sequencer: " << m_version 784 << ", outstanding requests: " << m_outstanding_count 785 << ", read request table: " << m_readRequestTable 786 << ", write request table: " << m_writeRequestTable 787 << "]"; 788} 789 790// this can be called from setState whenever coherence permissions are 791// upgraded when invoked, coherence violations will be checked for the 792// given block 793void 794Sequencer::checkCoherence(const Address& addr) 795{ 796#ifdef CHECK_COHERENCE 797 g_system_ptr->checkGlobalCoherenceInvariant(addr); 798#endif 799} 800 801void 802Sequencer::recordRequestType(SequencerRequestType requestType) { 803 DPRINTF(RubyStats, "Recorded statistic: %s\n", 804 SequencerRequestType_to_string(requestType)); 805} 806 807 808void 809Sequencer::evictionCallback(const Address& address) 810{ 811 ruby_eviction_callback(address); 812} 813